[{"id":1865289,"web_url":"http://patchwork.ozlabs.org/comment/1865289/","msgid":"","list_archive_url":null,"date":"2018-02-27T22:37:05","subject":"Re: [Qemu-devel] [PATCH v5 4/7] hw/mdio: Mask out read-only bits.","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Fri, Sep 22, 2017 at 10:13 AM, Philippe Mathieu-Daudé\n wrote:\n> From: Grant Likely \n>\n> The RST and ANEG_RST bits are commands, not settings. An operating\n> system will get confused (or at least u-boot does) if those bits remain\n> set after writing to them. Therefore, mask them out on write.\n>\n> Similarly, no bits in the ID1, ID2, and remote capability registers are\n> writeable; so mask them out also.\n>\n> Signed-off-by: Grant Likely \n> Signed-off-by: Philippe Mathieu-Daudé \n> [PMD: just rebased]\n> ---\n> include/hw/net/mdio.h | 1 +\n> hw/net/mdio.c | 16 ++++++++++++----\n> 2 files changed, 13 insertions(+), 4 deletions(-)\n>\n> diff --git a/include/hw/net/mdio.h b/include/hw/net/mdio.h\n> index b3b4f497c0..ed1879a728 100644\n> --- a/include/hw/net/mdio.h\n> +++ b/include/hw/net/mdio.h\n> @@ -53,6 +53,7 @@\n>\n> struct qemu_phy {\n> uint32_t regs[NUM_PHY_REGS];\n> + const uint16_t *regs_readonly_mask; /* 0=writable, 1=read-only */\n>\n> int link;\n>\n> diff --git a/hw/net/mdio.c b/hw/net/mdio.c\n> index 33bfbb4623..89a6a3a590 100644\n> --- a/hw/net/mdio.c\n> +++ b/hw/net/mdio.c\n> @@ -109,17 +109,24 @@ static unsigned int mdio_phy_read(struct qemu_phy *phy, unsigned int req)\n>\n> static void mdio_phy_write(struct qemu_phy *phy, unsigned int req, unsigned int data)\n> {\n> - int regnum;\n> + int regnum = req & 0x1f;\n> + uint16_t mask = phy->regs_readonly_mask[regnum];\n>\n> - regnum = req & 0x1f;\n> - D(printf(\"%s reg[%d] = %x\\n\", __func__, regnum, data));\n> + D(printf(\"%s reg[%d] = %x; mask=%x\\n\", __func__, regnum, data, mask));\n> switch (regnum) {\n> default:\n> - phy->regs[regnum] = data;\n> + phy->regs[regnum] = (phy->regs[regnum] & mask) | (data & ~mask);\n> break;\n> }\n> }\n>\n> +static const uint16_t default_readonly_mask[32] = {\n> + [PHY_CTRL] = PHY_CTRL_RST | PHY_CTRL_ANEG_RST,\n> + [PHY_ID1] = 0xffff,\n> + [PHY_ID2] = 0xffff,\n> + [PHY_LP_ABILITY] = 0xffff,\n> +};\n\nThis is what the register API is really good at :)\n\nOverall this looks fine, can we use a macro for the 32 though and then\nprotect accesses with an assert() or if()?\n\nAlistair\n\n> +\n> void mdio_phy_init(struct qemu_phy *phy, uint16_t id1, uint16_t id2)\n> {\n> phy->regs[PHY_CTRL] = 0x3100;\n> @@ -128,6 +135,7 @@ void mdio_phy_init(struct qemu_phy *phy, uint16_t id1, uint16_t id2)\n> phy->regs[PHY_ID2] = id2;\n> /* Autonegotiation advertisement reg. */\n> phy->regs[PHY_AUTONEG_ADV] = 0x01e1;\n> + phy->regs_readonly_mask = default_readonly_mask;\n> phy->link = 1;\n>\n> phy->read = mdio_phy_read;\n> --\n> 2.14.1\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:4010:c07::241","Subject":"Re: [Qemu-devel] [PATCH v5 4/7] hw/mdio: Mask out read-only bits.","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell ,\n\tJason Wang , Grant Likely ,\n\t\"qemu-devel@nongnu.org Developers\" ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]