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GET /api/patches/817573/?format=api
{ "id": 817573, "url": "http://patchwork.ozlabs.org/api/patches/817573/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-14-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506092407-26985-14-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-22T15:00:00", "name": "[13/20] nvic: Implement Security Attribution Unit registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cb306789bd2991dc8401474d91e85033488c24a6", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-14-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 4650, "url": "http://patchwork.ozlabs.org/api/series/4650/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4650", "date": "2017-09-22T14:59:47", "name": "ARM v8M: exception entry, exit and security", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4650/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817573/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817573/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzH5b14XXz9sNw\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 23 Sep 2017 01:12:19 +1000 (AEST)", "from localhost ([::1]:59386 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dvPcn-0001ju-44\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 11:12:17 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:47244)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1dvPQg-00086K-GJ\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:50 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1dvPQe-0004G5-N9\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:46 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37568)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1dvPQa-00046S-9l; Fri, 22 Sep 2017 10:59:40 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1dvPQY-0007DU-Ln; Fri, 22 Sep 2017 15:59:38 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Fri, 22 Sep 2017 16:00:00 +0100", "Message-Id": "<1506092407-26985-14-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>", "References": "<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 13/20] nvic: Implement Security Attribution\n\tUnit registers", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Implement the register interface for the SAU: SAU_CTRL,\nSAU_TYPE, SAU_RNR, SAU_RBAR and SAU_RLAR. None of the\nactual behaviour is implemented here; registers just\nread back as written.\n\nWhen the CPU definition for Cortex-M33 is eventually\nadded, its initfn will set cpu->sau_sregion, in the same\nway that we currently set cpu->pmsav7_dregion for the\nM3 and M4.\n\nNumber of SAU regions is typically a configurable\nCPU parameter, but this patch doesn't provide a\nQEMU CPU property for it. We can easily add one when\nwe have a board that requires it.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/cpu.h | 10 +++++\n hw/intc/armv7m_nvic.c | 116 ++++++++++++++++++++++++++++++++++++++++++++++++++\n target/arm/cpu.c | 27 ++++++++++++\n target/arm/machine.c | 14 ++++++\n 4 files changed, 167 insertions(+)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 9e3a16d..441e584 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -568,6 +568,14 @@ typedef struct CPUARMState {\n uint32_t mair1[M_REG_NUM_BANKS];\n } pmsav8;\n \n+ /* v8M SAU */\n+ struct {\n+ uint32_t *rbar;\n+ uint32_t *rlar;\n+ uint32_t rnr;\n+ uint32_t ctrl;\n+ } sau;\n+\n void *nvic;\n const struct arm_boot_info *boot_info;\n /* Store GICv3CPUState to access from this struct */\n@@ -663,6 +671,8 @@ struct ARMCPU {\n bool has_mpu;\n /* PMSAv7 MPU number of supported regions */\n uint32_t pmsav7_dregion;\n+ /* v8M SAU number of supported regions */\n+ uint32_t sau_sregion;\n \n /* PSCI conduit used to invoke PSCI methods\n * 0 - disabled, 1 - smc, 2 - hvc\ndiff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex deea637..bd1d5d3 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -1017,6 +1017,60 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)\n goto bad_offset;\n }\n return cpu->env.pmsav8.mair1[attrs.secure];\n+ case 0xdd0: /* SAU_CTRL */\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ return 0;\n+ }\n+ return cpu->env.sau.ctrl;\n+ case 0xdd4: /* SAU_TYPE */\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ return 0;\n+ }\n+ return cpu->sau_sregion;\n+ case 0xdd8: /* SAU_RNR */\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ return 0;\n+ }\n+ return cpu->env.sau.rnr;\n+ case 0xddc: /* SAU_RBAR */\n+ {\n+ int region = cpu->env.sau.rnr;\n+\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ return 0;\n+ }\n+ if (region >= cpu->sau_sregion) {\n+ return 0;\n+ }\n+ return cpu->env.sau.rbar[region];\n+ }\n+ case 0xde0: /* SAU_RLAR */\n+ {\n+ int region = cpu->env.sau.rnr;\n+\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ return 0;\n+ }\n+ if (region >= cpu->sau_sregion) {\n+ return 0;\n+ }\n+ return cpu->env.sau.rlar[region];\n+ }\n case 0xde4: /* SFSR */\n if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n goto bad_offset;\n@@ -1384,6 +1438,68 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,\n * only affect cacheability, and we don't implement caching.\n */\n break;\n+ case 0xdd0: /* SAU_CTRL */\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ return;\n+ }\n+ cpu->env.sau.ctrl = value & 3;\n+ case 0xdd4: /* SAU_TYPE */\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ break;\n+ case 0xdd8: /* SAU_RNR */\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ return;\n+ }\n+ if (value >= cpu->sau_sregion) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"SAU region out of range %\"\n+ PRIu32 \"/%\" PRIu32 \"\\n\",\n+ value, cpu->sau_sregion);\n+ } else {\n+ cpu->env.sau.rnr = value;\n+ }\n+ break;\n+ case 0xddc: /* SAU_RBAR */\n+ {\n+ int region = cpu->env.sau.rnr;\n+\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ return;\n+ }\n+ if (region >= cpu->sau_sregion) {\n+ return;\n+ }\n+ cpu->env.sau.rbar[region] = value & ~0x1f;\n+ tlb_flush(CPU(cpu));\n+ break;\n+ }\n+ case 0xde0: /* SAU_RLAR */\n+ {\n+ int region = cpu->env.sau.rnr;\n+\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ return;\n+ }\n+ if (region >= cpu->sau_sregion) {\n+ return;\n+ }\n+ cpu->env.sau.rlar[region] = value & ~0x1c;\n+ tlb_flush(CPU(cpu));\n+ break;\n+ }\n case 0xde4: /* SFSR */\n if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n goto bad_offset;\ndiff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex 3344979..1627836 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -285,6 +285,18 @@ static void arm_cpu_reset(CPUState *s)\n env->pmsav8.mair1[M_REG_S] = 0;\n }\n \n+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {\n+ if (cpu->sau_sregion > 0) {\n+ memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);\n+ memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);\n+ }\n+ env->sau.rnr = 0;\n+ /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what\n+ * the Cortex-M33 does.\n+ */\n+ env->sau.ctrl = 0;\n+ }\n+\n set_flush_to_zero(1, &env->vfp.standard_fp_status);\n set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);\n set_default_nan_mode(1, &env->vfp.standard_fp_status);\n@@ -870,6 +882,20 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)\n }\n }\n \n+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {\n+ uint32_t nr = cpu->sau_sregion;\n+\n+ if (nr > 0xff) {\n+ error_setg(errp, \"v8M SAU #regions invalid %\" PRIu32, nr);\n+ return;\n+ }\n+\n+ if (nr) {\n+ env->sau.rbar = g_new0(uint32_t, nr);\n+ env->sau.rlar = g_new0(uint32_t, nr);\n+ }\n+ }\n+\n if (arm_feature(env, ARM_FEATURE_EL3)) {\n set_feature(env, ARM_FEATURE_VBAR);\n }\n@@ -1141,6 +1167,7 @@ static void cortex_m4_initfn(Object *obj)\n cpu->midr = 0x410fc240; /* r0p0 */\n cpu->pmsav7_dregion = 8;\n }\n+\n static void arm_v7m_class_init(ObjectClass *oc, void *data)\n {\n CPUClass *cc = CPU_CLASS(oc);\ndiff --git a/target/arm/machine.c b/target/arm/machine.c\nindex d4b3baf..a52d0f9 100644\n--- a/target/arm/machine.c\n+++ b/target/arm/machine.c\n@@ -242,6 +242,13 @@ static bool s_rnr_vmstate_validate(void *opaque, int version_id)\n return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion;\n }\n \n+static bool sau_rnr_vmstate_validate(void *opaque, int version_id)\n+{\n+ ARMCPU *cpu = opaque;\n+\n+ return cpu->env.sau.rnr < cpu->sau_sregion;\n+}\n+\n static bool m_security_needed(void *opaque)\n {\n ARMCPU *cpu = opaque;\n@@ -278,6 +285,13 @@ static const VMStateDescription vmstate_m_security = {\n VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU),\n VMSTATE_UINT32(env.v7m.sfsr, ARMCPU),\n VMSTATE_UINT32(env.v7m.sfar, ARMCPU),\n+ VMSTATE_VARRAY_UINT32(env.sau.rbar, ARMCPU, sau_sregion, 0,\n+ vmstate_info_uint32, uint32_t),\n+ VMSTATE_VARRAY_UINT32(env.sau.rlar, ARMCPU, sau_sregion, 0,\n+ vmstate_info_uint32, uint32_t),\n+ VMSTATE_UINT32(env.sau.rnr, ARMCPU),\n+ VMSTATE_VALIDATE(\"SAU_RNR is valid\", sau_rnr_vmstate_validate),\n+ VMSTATE_UINT32(env.sau.ctrl, ARMCPU),\n VMSTATE_END_OF_LIST()\n }\n };\n", "prefixes": [ "13/20" ] }