[{"id":1780896,"web_url":"http://patchwork.ozlabs.org/comment/1780896/","msgid":"<0c54401b-10b5-9d2b-4a7e-51e9a40f2408@linaro.org>","list_archive_url":null,"date":"2017-10-05T18:33:23","subject":"Re: [Qemu-devel] [PATCH 13/20] nvic: Implement Security Attribution\n\tUnit registers","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/22/2017 11:00 AM, Peter Maydell wrote:\n> Implement the register interface for the SAU: SAU_CTRL,\n> SAU_TYPE, SAU_RNR, SAU_RBAR and SAU_RLAR. None of the\n> actual behaviour is implemented here; registers just\n> read back as written.\n> \n> When the CPU definition for Cortex-M33 is eventually\n> added, its initfn will set cpu->sau_sregion, in the same\n> way that we currently set cpu->pmsav7_dregion for the\n> M3 and M4.\n> \n> Number of SAU regions is typically a configurable\n> CPU parameter, but this patch doesn't provide a\n> QEMU CPU property for it. We can easily add one when\n> we have a board that requires it.\n> \n> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>\n> ---\n>  target/arm/cpu.h      |  10 +++++\n>  hw/intc/armv7m_nvic.c | 116 ++++++++++++++++++++++++++++++++++++++++++++++++++\n>  target/arm/cpu.c      |  27 ++++++++++++\n>  target/arm/machine.c  |  14 ++++++\n>  4 files changed, 167 insertions(+)\n\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\n\n\nr~","headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"cn2hhzpJ\"; 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\n\tThu, 05 Oct 2017 11:33:26 -0700 (PDT)","To":"Peter Maydell <peter.maydell@linaro.org>, qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org","References":"<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>\n\t<1506092407-26985-14-git-send-email-peter.maydell@linaro.org>","From":"Richard Henderson <richard.henderson@linaro.org>","Message-ID":"<0c54401b-10b5-9d2b-4a7e-51e9a40f2408@linaro.org>","Date":"Thu, 5 Oct 2017 14:33:23 -0400","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506092407-26985-14-git-send-email-peter.maydell@linaro.org>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::22a","Subject":"Re: [Qemu-devel] [PATCH 13/20] nvic: Implement Security Attribution\n\tUnit registers","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"<qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<http://lists.nongnu.org/archive/html/qemu-devel/>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Cc":"patches@linaro.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>"}}]