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GET /api/patches/817568/?format=api
{ "id": 817568, "url": "http://patchwork.ozlabs.org/api/patches/817568/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-17-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506092407-26985-17-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-22T15:00:03", "name": "[16/20] target/arm: Factor out \"get mmuidx for specified security state\"", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ecd33832e35a07f63b2d1a227980d0a046abcdd4", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-17-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 4650, "url": "http://patchwork.ozlabs.org/api/series/4650/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4650", "date": "2017-09-22T14:59:47", "name": "ARM v8M: exception entry, exit and security", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4650/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817568/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817568/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzH035lf8z9sNw\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 23 Sep 2017 01:07:31 +1000 (AEST)", "from localhost ([::1]:59354 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dvPY9-0005j0-Qw\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 11:07:29 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:47242)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1dvPQg-00086E-E0\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:50 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1dvPQf-0004HD-ER\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:46 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37574)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1dvPQc-00049B-Sd; Fri, 22 Sep 2017 10:59:43 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1dvPQa-0007F6-Tc; Fri, 22 Sep 2017 15:59:40 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Fri, 22 Sep 2017 16:00:03 +0100", "Message-Id": "<1506092407-26985-17-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>", "References": "<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 16/20] target/arm: Factor out \"get mmuidx for\n\tspecified security state\"", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "For the SG instruction and secure function return we are going\nto want to do memory accesses using the MMU index of the CPU\nin secure state, even though the CPU is currently in non-secure\nstate. Write arm_v7m_mmu_idx_for_secstate() to do this job,\nand use it in cpu_mmu_index().\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/cpu.h | 32 +++++++++++++++++++++-----------\n 1 file changed, 21 insertions(+), 11 deletions(-)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 70c1f85..89d49cd 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -2329,23 +2329,33 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)\n }\n }\n \n+/* Return the MMU index for a v7M CPU in the specified security state */\n+static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,\n+ bool secstate)\n+{\n+ int el = arm_current_el(env);\n+ ARMMMUIdx mmu_idx;\n+\n+ if (el == 0) {\n+ mmu_idx = secstate ? ARMMMUIdx_MSUser : ARMMMUIdx_MUser;\n+ } else {\n+ mmu_idx = secstate ? ARMMMUIdx_MSPriv : ARMMMUIdx_MPriv;\n+ }\n+\n+ if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {\n+ mmu_idx = secstate ? ARMMMUIdx_MSNegPri : ARMMMUIdx_MNegPri;\n+ }\n+\n+ return mmu_idx;\n+}\n+\n /* Determine the current mmu_idx to use for normal loads/stores */\n static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)\n {\n int el = arm_current_el(env);\n \n if (arm_feature(env, ARM_FEATURE_M)) {\n- ARMMMUIdx mmu_idx;\n-\n- if (el == 0) {\n- mmu_idx = env->v7m.secure ? ARMMMUIdx_MSUser : ARMMMUIdx_MUser;\n- } else {\n- mmu_idx = env->v7m.secure ? ARMMMUIdx_MSPriv : ARMMMUIdx_MPriv;\n- }\n-\n- if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) {\n- mmu_idx = env->v7m.secure ? ARMMMUIdx_MSNegPri : ARMMMUIdx_MNegPri;\n- }\n+ ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);\n \n return arm_to_core_mmu_idx(mmu_idx);\n }\n", "prefixes": [ "16/20" ] }