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GET /api/patches/817565/?format=api
{ "id": 817565, "url": "http://patchwork.ozlabs.org/api/patches/817565/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-7-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506092407-26985-7-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-22T14:59:53", "name": "[06/20] target/arm: Check for xPSR mismatch usage faults earlier for v8M", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "47a2b62e89098c52afe26aaff20079e674146a55", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1506092407-26985-7-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 4650, "url": "http://patchwork.ozlabs.org/api/series/4650/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=4650", "date": "2017-09-22T14:59:47", "name": "ARM v8M: exception entry, exit and security", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4650/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817565/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817565/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzGxd0WZrz9sPm\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 23 Sep 2017 01:05:25 +1000 (AEST)", "from localhost ([::1]:59342 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dvPW7-0003lD-1T\n\tfor incoming@patchwork.ozlabs.org; Fri, 22 Sep 2017 11:05:23 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:46961)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1dvPQY-0007wN-Gd\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:39 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1dvPQX-000454-Fu\n\tfor qemu-devel@nongnu.org; Fri, 22 Sep 2017 10:59:38 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37550)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1dvPQV-00041E-0K; Fri, 22 Sep 2017 10:59:35 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1dvPQT-00079n-Rq; Fri, 22 Sep 2017 15:59:33 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Fri, 22 Sep 2017 15:59:53 +0100", "Message-Id": "<1506092407-26985-7-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>", "References": "<1506092407-26985-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 06/20] target/arm: Check for xPSR mismatch\n\tusage faults earlier for v8M", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "ARM v8M specifies that the INVPC usage fault for mismatched\nxPSR exception field and handler mode bit should be checked\nbefore updating the PSR and SP, so that the fault is taken\nwith the existing stack frame rather than by pushing a new one.\nPerform this check in the right place for v8M.\n\nSince v7M specifies in its pseudocode that this usage fault\ncheck should happen later, we have to retain the original\ncode for that check rather than being able to merge the two.\n(The distinction is architecturally visible but only in\nvery obscure corner cases like attempting an invalid exception\nreturn with an exception frame in read only memory.)\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/helper.c | 30 +++++++++++++++++++++++++++---\n 1 file changed, 27 insertions(+), 3 deletions(-)", "diff": "diff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 4444d04..a2e46fb 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6426,6 +6426,29 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n }\n xpsr = ldl_phys(cs->as, frameptr + 0x1c);\n \n+ if (arm_feature(env, ARM_FEATURE_V8)) {\n+ /* For v8M we have to check whether the xPSR exception field\n+ * matches the EXCRET value for return to handler/thread\n+ * before we commit to changing the SP and xPSR.\n+ */\n+ bool will_be_handler = (xpsr & XPSR_EXCP) != 0;\n+ if (return_to_handler != will_be_handler) {\n+ /* Take an INVPC UsageFault on the current stack.\n+ * By this point we will have switched to the security state\n+ * for the background state, so this UsageFault will target\n+ * that state.\n+ */\n+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,\n+ env->v7m.secure);\n+ env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;\n+ v7m_exception_taken(cpu, excret);\n+ qemu_log_mask(CPU_LOG_INT, \"...taking UsageFault on existing \"\n+ \"stackframe: failed exception return integrity \"\n+ \"check\\n\");\n+ return;\n+ }\n+ }\n+\n /* Commit to consuming the stack frame */\n frameptr += 0x20;\n /* Undo stack alignment (the SPREALIGN bit indicates that the original\n@@ -6445,12 +6468,13 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n /* The restored xPSR exception field will be zero if we're\n * resuming in Thread mode. If that doesn't match what the\n * exception return excret specified then this is a UsageFault.\n+ * v7M requires we make this check here; v8M did it earlier.\n */\n if (return_to_handler != arm_v7m_is_handler_mode(env)) {\n- /* Take an INVPC UsageFault by pushing the stack again.\n- * TODO: the v8M version of this code should target the\n- * background state for this exception.\n+ /* Take an INVPC UsageFault by pushing the stack again;\n+ * we know we're v7M so this is never a Secure UsageFault.\n */\n+ assert(!arm_feature(env, ARM_FEATURE_V8));\n armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false);\n env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;\n v7m_push_stack(cpu);\n", "prefixes": [ "06/20" ] }