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GET /api/patches/817445/?format=api
{ "id": 817445, "url": "http://patchwork.ozlabs.org/api/patches/817445/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170922114703.30511-2-maxime.ripard@free-electrons.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170922114703.30511-2-maxime.ripard@free-electrons.com>", "list_archive_url": null, "date": "2017-09-22T11:47:02", "name": "[1/2] dt-bindings: media: Add Cadence MIPI-CSI2 TX Device Tree bindings", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "a3cd0174923d0be2f51a1034947d78e710275e6b", "submitter": { "id": 12916, "url": "http://patchwork.ozlabs.org/api/people/12916/?format=api", "name": "Maxime Ripard", "email": "maxime.ripard@free-electrons.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170922114703.30511-2-maxime.ripard@free-electrons.com/mbox/", "series": [ { "id": 4603, "url": "http://patchwork.ozlabs.org/api/series/4603/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4603", "date": "2017-09-22T11:47:01", "name": "media: v4l: Add support for the Cadence MIPI-CSI2 TX controller", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4603/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817445/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817445/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xzBY8218Pz9sP1\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 21:47:24 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752317AbdIVLrX (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tFri, 22 Sep 2017 07:47:23 -0400", "from mail.free-electrons.com ([62.4.15.54]:59895 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752313AbdIVLrW (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Fri, 22 Sep 2017 07:47:22 -0400", "by mail.free-electrons.com (Postfix, from userid 110)\n\tid 53B8F209B1; Fri, 22 Sep 2017 13:47:20 +0200 (CEST)", "from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id C8238208D1;\n\tFri, 22 Sep 2017 13:47:05 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0", "From": "Maxime Ripard <maxime.ripard@free-electrons.com>", "To": "Mauro Carvalho Chehab <mchehab@kernel.org>,\n\tMark Rutland <mark.rutland@arm.com>, Rob Herring <robh+dt@kernel.org>", "Cc": "Laurent Pinchart <laurent.pinchart@ideasonboard.com>,\n\tlinux-media@vger.kernel.org, devicetree@vger.kernel.org, Cyprian Wronka\n\t<cwronka@cadence.com>, Richard Sproul <sproul@cadence.com>, Alan Douglas\n\t<adouglas@cadence.com>, Steve Creaney <screaney@cadence.com>, Thomas\n\tPetazzoni <thomas.petazzoni@free-electrons.com>, Boris Brezillon\n\t<boris.brezillon@free-electrons.com>, =?utf-8?q?Niklas_S=C3=B6derlund?=\n\t<niklas.soderlund@ragnatech.se>, Hans Verkuil <hans.verkuil@cisco.com>,\n\tSakari Ailus <sakari.ailus@linux.intel.com>, \n\tBenoit Parrot <bparrot@ti.com>, nm@ti.com,\n\tMaxime Ripard <maxime.ripard@free-electrons.com>", "Subject": "[PATCH 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 TX Device Tree\n\tbindings", "Date": "Fri, 22 Sep 2017 13:47:02 +0200", "Message-Id": "<20170922114703.30511-2-maxime.ripard@free-electrons.com>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170922114703.30511-1-maxime.ripard@free-electrons.com>", "References": "<20170922114703.30511-1-maxime.ripard@free-electrons.com>", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "The Cadence MIPI-CSI2 RX controller is a CSI2 bridge that supports up to 4\nvideo streams and can output on up to 4 CSI-2 lanes, depending on the\nhardware implementation.\n\nIt can operate with an external D-PHY, an internal one or no D-PHY at all\nin some configurations.\n\nSigned-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>\n---\n .../devicetree/bindings/media/cdns,csi2tx.txt | 97 ++++++++++++++++++++++\n 1 file changed, 97 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2tx.txt", "diff": "diff --git a/Documentation/devicetree/bindings/media/cdns,csi2tx.txt b/Documentation/devicetree/bindings/media/cdns,csi2tx.txt\nnew file mode 100644\nindex 000000000000..5fb70bba910e\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/media/cdns,csi2tx.txt\n@@ -0,0 +1,97 @@\n+Cadence MIPI-CSI2 TX controller\n+===============================\n+\n+The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to\n+4 CSI lanes in output, and up to 4 different pixel streams in input.\n+\n+Required properties:\n+ - compatible: must be set to \"cdns,csi2tx\"\n+ - reg: base address and size of the memory mapped region\n+ - clocks: phandles to the clocks driving the controller\n+ - clock-names: must contain:\n+ * esc_clk: escape mode clock\n+ * p_clk: register bank clock\n+ * pixel_if[0-3]_clk: pixel stream output clock, one for each stream\n+ implemented in hardware, between 0 and 3\n+\n+Optional properties\n+ - phys: phandle to the D-PHY. If it is set, phy-names need to be set\n+ - phy-names: must contain dphy\n+\n+Required subnodes:\n+ - ports: A ports node with one port child node per device input and output\n+ port, in accordance with the video interface bindings defined in\n+ Documentation/devicetree/bindings/media/video-interfaces.txt. The\n+ port nodes numbered as follows.\n+\n+ Port Description\n+ -----------------------------\n+ 0 CSI-2 output\n+ 1 Stream 0 input\n+ 2 Stream 1 input\n+ 3 Stream 2 input\n+ 4 Stream 3 input\n+\n+ The stream input port nodes are optional if they are not\n+ connected to anything at the hardware level or implemented\n+ in the design.\n+\n+Example:\n+\n+csi2tx: csi-bridge@0d0e1000 {\n+\tcompatible = \"cdns,csi2tx\";\n+\treg = <0x0d0e1000 0x1000>;\n+\tclocks = <&byteclock>, <&byteclock>,\n+\t\t <&coreclock>, <&coreclock>,\n+\t\t <&coreclock>, <&coreclock>;\n+\tclock-names = \"p_clk\", \"esc_clk\",\n+\t\t \"pixel_if0_clk\", \"pixel_if1_clk\",\n+\t\t \"pixel_if2_clk\", \"pixel_if3_clk\";\n+\n+\tports {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\n+\t\t\tcsi2tx_out: endpoint {\n+\t\t\t\tremote-endpoint = <&remote_in>;\n+\t\t\t\tclock-lanes = <0>;\n+\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\n+\t\t\tcsi2tx_in_stream0: endpoint {\n+\t\t\t\tremote-endpoint = <&stream0_out>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\n+\t\t\tcsi2tx_in_stream1: endpoint {\n+\t\t\t\tremote-endpoint = <&stream1_out>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\n+\t\t\tcsi2tx_in_stream2: endpoint {\n+\t\t\t\tremote-endpoint = <&stream2_out>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\n+\t\t\tcsi2tx_in_stream3: endpoint {\n+\t\t\t\tremote-endpoint = <&stream3_out>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n", "prefixes": [ "1/2" ] }