[{"id":1773526,"web_url":"http://patchwork.ozlabs.org/comment/1773526/","msgid":"<20170922120106.mfxoh34anazqakvz@valkosipuli.retiisi.org.uk>","list_archive_url":null,"date":"2017-09-22T12:01:06","subject":"Re: [PATCH 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 TX Device\n\tTree bindings","submitter":{"id":1593,"url":"http://patchwork.ozlabs.org/api/people/1593/","name":"Sakari Ailus","email":"sakari.ailus@iki.fi"},"content":"On Fri, Sep 22, 2017 at 01:47:02PM +0200, Maxime Ripard wrote:\n> The Cadence MIPI-CSI2 RX controller is a CSI2 bridge that supports up to 4\n\nShould this be TX?\n\nI was just thinking what does this chip do, and saw both. RX it at least\nless common. :-)","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xzBs44j1Dz9sPk\n\tfor ;\n\tFri, 22 Sep 2017 22:01:12 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752162AbdIVMBK (ORCPT\n\t);\n\tFri, 22 Sep 2017 08:01:10 -0400","from nblzone-211-213.nblnetworks.fi ([83.145.211.213]:43864 \"EHLO\n\thillosipuli.retiisi.org.uk\" rhost-flags-OK-OK-OK-FAIL)\n\tby vger.kernel.org with ESMTP id S1752131AbdIVMBJ (ORCPT\n\t); Fri, 22 Sep 2017 08:01:09 -0400","from valkosipuli.localdomain (valkosipuli.retiisi.org.uk\n\t[IPv6:2001:1bc8:1a6:d3d5::80:2])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby hillosipuli.retiisi.org.uk (Postfix) with ESMTPS id 45965600E1;\n\tFri, 22 Sep 2017 15:01:07 +0300 (EEST)","from sakke by valkosipuli.localdomain with local (Exim 4.89)\n\t(envelope-from )\n\tid 1dvMdm-0005fJ-RF; Fri, 22 Sep 2017 15:01:06 +0300"],"Date":"Fri, 22 Sep 2017 15:01:06 +0300","From":"Sakari Ailus ","To":"Maxime Ripard ","Cc":"Mauro Carvalho Chehab , Mark Rutland\n\t, Rob Herring , Laurent\n\tPinchart , \n\tlinux-media@vger.kernel.org, devicetree@vger.kernel.org, Cyprian Wronka\n\t, Richard Sproul , Alan Douglas\n\t, Steve Creaney , Thomas\n\tPetazzoni , Boris Brezillon\n\t, Niklas =?iso-8859-1?q?S=F6derlun?=\n\t=?iso-8859-1?q?d?= ,\n\tHans Verkuil , Sakari Ailus\n\t, \n\tBenoit Parrot , nm@ti.com","Subject":"Re: [PATCH 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 TX Device\n\tTree bindings","Message-ID":"<20170922120106.mfxoh34anazqakvz@valkosipuli.retiisi.org.uk>","References":"<20170922114703.30511-1-maxime.ripard@free-electrons.com>\n\t<20170922114703.30511-2-maxime.ripard@free-electrons.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170922114703.30511-2-maxime.ripard@free-electrons.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1773687,"web_url":"http://patchwork.ozlabs.org/comment/1773687/","msgid":"<20170922145214.u245ka35az5ewthm@flea.lan>","list_archive_url":null,"date":"2017-09-22T14:52:14","subject":"Re: [PATCH 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 TX Device\n\tTree bindings","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"Hi Sakari,\n\nOn Fri, Sep 22, 2017 at 12:01:06PM +0000, Sakari Ailus wrote:\n> On Fri, Sep 22, 2017 at 01:47:02PM +0200, Maxime Ripard wrote:\n> > The Cadence MIPI-CSI2 RX controller is a CSI2 bridge that supports up to 4\n> \n> Should this be TX?\n> \n> I was just thinking what does this chip do, and saw both. RX it at least\n> less common. :-)\n\nYes, definitely :)\n\nThis one's a transceiver, the other one a receiver.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xzGfV1TFsz9s7p\n\tfor ;\n\tSat, 23 Sep 2017 00:52:18 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752496AbdIVOwQ (ORCPT\n\t);\n\tFri, 22 Sep 2017 10:52:16 -0400","from mail.free-electrons.com ([62.4.15.54]:38442 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752453AbdIVOwQ (ORCPT\n\t); Fri, 22 Sep 2017 10:52:16 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 27558209FC; Fri, 22 Sep 2017 16:52:14 +0200 (CEST)","from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id F36AF209FA;\n\tFri, 22 Sep 2017 16:52:13 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Fri, 22 Sep 2017 16:52:14 +0200","From":"Maxime Ripard ","To":"Sakari Ailus ","Cc":"Mauro Carvalho Chehab , Mark Rutland\n\t, Rob Herring , Laurent\n\tPinchart , \n\tlinux-media@vger.kernel.org, devicetree@vger.kernel.org, Cyprian Wronka\n\t, Richard Sproul , Alan Douglas\n\t, Steve Creaney , Thomas\n\tPetazzoni , Boris Brezillon\n\t, Niklas =?iso-8859-1?q?S=F6derlun?=\n\t=?iso-8859-1?q?d?= ,\n\tHans Verkuil , Sakari Ailus\n\t, \n\tBenoit Parrot , nm@ti.com","Subject":"Re: [PATCH 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 TX Device\n\tTree bindings","Message-ID":"<20170922145214.u245ka35az5ewthm@flea.lan>","References":"<20170922114703.30511-1-maxime.ripard@free-electrons.com>\n\t<20170922114703.30511-2-maxime.ripard@free-electrons.com>\n\t<20170922120106.mfxoh34anazqakvz@valkosipuli.retiisi.org.uk>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"yvg77p54kzhem33d\"","Content-Disposition":"inline","In-Reply-To":"<20170922120106.mfxoh34anazqakvz@valkosipuli.retiisi.org.uk>","User-Agent":"NeoMutt/20170914 (1.9.0)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1779290,"web_url":"http://patchwork.ozlabs.org/comment/1779290/","msgid":"<20171003220153.mxjwzmcejwojevlg@rob-hp-laptop>","list_archive_url":null,"date":"2017-10-03T22:01:53","subject":"Re: [PATCH 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 TX Device\n\tTree bindings","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Fri, Sep 22, 2017 at 01:47:02PM +0200, Maxime Ripard wrote:\n> The Cadence MIPI-CSI2 RX controller is a CSI2 bridge that supports up to 4\n> video streams and can output on up to 4 CSI-2 lanes, depending on the\n> hardware implementation.\n> \n> It can operate with an external D-PHY, an internal one or no D-PHY at all\n> in some configurations.\n> \n> Signed-off-by: Maxime Ripard \n> ---\n> .../devicetree/bindings/media/cdns,csi2tx.txt | 97 ++++++++++++++++++++++\n> 1 file changed, 97 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2tx.txt\n\nOther than the one issue pointed out,\n\nAcked-by: Rob Herring \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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