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GET /api/patches/817437/?format=api
{ "id": 817437, "url": "http://patchwork.ozlabs.org/api/patches/817437/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170922100823.18184-2-maxime.ripard@free-electrons.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170922100823.18184-2-maxime.ripard@free-electrons.com>", "list_archive_url": null, "date": "2017-09-22T10:08:22", "name": "[v4,1/2] dt-bindings: media: Add Cadence MIPI-CSI2 RX Device Tree bindings", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "803f1eb7a40c0ca1a2672d4b5aea6cf65ebb98c1", "submitter": { "id": 12916, "url": "http://patchwork.ozlabs.org/api/people/12916/?format=api", "name": "Maxime Ripard", "email": "maxime.ripard@free-electrons.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170922100823.18184-2-maxime.ripard@free-electrons.com/mbox/", "series": [ { "id": 4597, "url": "http://patchwork.ozlabs.org/api/series/4597/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4597", "date": "2017-09-22T10:08:22", "name": "media: v4l: Add support for the Cadence MIPI-CSI2 RX", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/4597/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817437/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817437/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xz9l2176Vz9sNw\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 21:10:54 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751985AbdIVLKw (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tFri, 22 Sep 2017 07:10:52 -0400", "from mail.free-electrons.com ([62.4.15.54]:58788 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751919AbdIVLKv (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Fri, 22 Sep 2017 07:10:51 -0400", "by mail.free-electrons.com (Postfix, from userid 110)\n\tid CCC05209DB; Fri, 22 Sep 2017 13:10:48 +0200 (CEST)", "from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id A1201208ED;\n\tFri, 22 Sep 2017 13:10:48 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0", "From": "Maxime Ripard <maxime.ripard@free-electrons.com>", "To": "Mauro Carvalho Chehab <mchehab@kernel.org>,\n\tMark Rutland <mark.rutland@arm.com>, Rob Herring <robh+dt@kernel.org>", "Cc": "Laurent Pinchart <laurent.pinchart@ideasonboard.com>,\n\tlinux-media@vger.kernel.org, devicetree@vger.kernel.org, Cyprian Wronka\n\t<cwronka@cadence.com>, Richard Sproul <sproul@cadence.com>, Alan Douglas\n\t<adouglas@cadence.com>, Steve Creaney <screaney@cadence.com>, Thomas\n\tPetazzoni <thomas.petazzoni@free-electrons.com>, Boris Brezillon\n\t<boris.brezillon@free-electrons.com>, =?utf-8?q?Niklas_S=C3=B6derlund?=\n\t<niklas.soderlund@ragnatech.se>, Hans Verkuil <hans.verkuil@cisco.com>,\n\tSakari Ailus <sakari.ailus@linux.intel.com>, \n\tBenoit Parrot <bparrot@ti.com>, nm@ti.com,\n\tMaxime Ripard <maxime.ripard@free-electrons.com>", "Subject": "[PATCH v4 1/2] dt-bindings: media: Add Cadence MIPI-CSI2 RX Device\n\tTree bindings", "Date": "Fri, 22 Sep 2017 12:08:22 +0200", "Message-Id": "<20170922100823.18184-2-maxime.ripard@free-electrons.com>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170922100823.18184-1-maxime.ripard@free-electrons.com>", "References": "<20170922100823.18184-1-maxime.ripard@free-electrons.com>", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to\n4 CSI-2 lanes, and can route the frames to up to 4 streams, depending on\nthe hardware implementation.\n\nIt can operate with an external D-PHY, an internal one or no D-PHY at all\nin some configurations.\n\nAcked-by: Rob Herring <robh@kernel.org>\nAcked-by: Benoit Parrot <bparrot@ti.com>\nAcked-by: Sakari Ailus <sakari.ailus@linux.intel.com>\nReviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>\nSigned-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>\n---\n .../devicetree/bindings/media/cdns,csi2rx.txt | 97 ++++++++++++++++++++++\n 1 file changed, 97 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/media/cdns,csi2rx.txt", "diff": "diff --git a/Documentation/devicetree/bindings/media/cdns,csi2rx.txt b/Documentation/devicetree/bindings/media/cdns,csi2rx.txt\nnew file mode 100644\nindex 000000000000..e9c30f964a96\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.txt\n@@ -0,0 +1,97 @@\n+Cadence MIPI-CSI2 RX controller\n+===============================\n+\n+The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI\n+lanes in input, and 4 different pixel streams in output.\n+\n+Required properties:\n+ - compatible: must be set to \"cdns,csi2rx\" and an SoC-specific compatible\n+ - reg: base address and size of the memory mapped region\n+ - clocks: phandles to the clocks driving the controller\n+ - clock-names: must contain:\n+ * sys_clk: main clock\n+ * p_clk: register bank clock\n+ * pixel_if[0-3]_clk: pixel stream output clock, one for each stream\n+ implemented in hardware, between 0 and 3\n+\n+Optional properties:\n+ - phys: phandle to the external D-PHY, phy-names must be provided\n+ - phy-names: must contain dphy, if the implementation uses an\n+ external D-PHY\n+\n+Required subnodes:\n+ - ports: A ports node with one port child node per device input and output\n+ port, in accordance with the video interface bindings defined in\n+ Documentation/devicetree/bindings/media/video-interfaces.txt. The\n+ port nodes numbered as follows.\n+\n+ Port Description\n+ -----------------------------\n+ 0 CSI-2 input\n+ 1 Stream 0 output\n+ 2 Stream 1 output\n+ 3 Stream 2 output\n+ 4 Stream 3 output\n+\n+ The stream output port nodes are optional if they are not connected\n+ to anything at the hardware level or implemented in the design.\n+\n+Example:\n+\n+csi2rx: csi-bridge@0d060000 {\n+\tcompatible = \"cdns,csi2rx\";\n+\treg = <0x0d060000 0x1000>;\n+\tclocks = <&byteclock>, <&byteclock>\n+\t\t <&coreclock>, <&coreclock>,\n+\t\t <&coreclock>, <&coreclock>;\n+\tclock-names = \"sys_clk\", \"p_clk\",\n+\t\t \"pixel_if0_clk\", \"pixel_if1_clk\",\n+\t\t \"pixel_if2_clk\", \"pixel_if3_clk\";\n+\n+\tports {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tport@0 {\n+\t\t\treg = <0>;\n+\n+\t\t\tcsi2rx_in_sensor: endpoint {\n+\t\t\t\tremote-endpoint = <&sensor_out_csi2rx>;\n+\t\t\t\tclock-lanes = <0>;\n+\t\t\t\tdata-lanes = <1 2>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@1 {\n+\t\t\treg = <1>;\n+\n+\t\t\tcsi2rx_out_grabber0: endpoint {\n+\t\t\t\tremote-endpoint = <&grabber0_in_csi2rx>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@2 {\n+\t\t\treg = <2>;\n+\n+\t\t\tcsi2rx_out_grabber1: endpoint {\n+\t\t\t\tremote-endpoint = <&grabber1_in_csi2rx>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@3 {\n+\t\t\treg = <3>;\n+\n+\t\t\tcsi2rx_out_grabber2: endpoint {\n+\t\t\t\tremote-endpoint = <&grabber2_in_csi2rx>;\n+\t\t\t};\n+\t\t};\n+\n+\t\tport@4 {\n+\t\t\treg = <4>;\n+\n+\t\t\tcsi2rx_out_grabber3: endpoint {\n+\t\t\t\tremote-endpoint = <&grabber3_in_csi2rx>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n", "prefixes": [ "v4", "1/2" ] }