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GET /api/patches/817363/?format=api
{ "id": 817363, "url": "http://patchwork.ozlabs.org/api/patches/817363/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170922072522.36306-2-Zhiqiang.Hou@nxp.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170922072522.36306-2-Zhiqiang.Hou@nxp.com>", "list_archive_url": null, "date": "2017-09-22T07:25:21", "name": "[1/2] PCI: Disable MSI for Freescale PCIe RC mode", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "c7cb4a9e50c6bb9fbd57a9610833d5cc2b4128df", "submitter": { "id": 67929, "url": "http://patchwork.ozlabs.org/api/people/67929/?format=api", "name": "Z.Q. Hou", "email": "zhiqiang.hou@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20170922072522.36306-2-Zhiqiang.Hou@nxp.com/mbox/", "series": [ { "id": 4558, "url": "http://patchwork.ozlabs.org/api/series/4558/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=4558", "date": "2017-09-22T07:25:22", "name": "PCI: layerscape: add fixes for layerscape-pcie errata", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4558/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817363/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817363/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "spf=fail (sender IP is 192.88.168.50)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xz57z1cQ2z9sPm\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 17:43:43 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751851AbdIVHnA (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tFri, 22 Sep 2017 03:43:00 -0400", "from mail-dm3nam03on0072.outbound.protection.outlook.com\n\t([104.47.41.72]:19201\n\t\"EHLO NAM03-DM3-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1751795AbdIVHmz (ORCPT <rfc822;linux-pci@vger.kernel.org>);\n\tFri, 22 Sep 2017 03:42:55 -0400", "from DM5PR03CA0040.namprd03.prod.outlook.com (10.174.189.157) by\n\tBN3PR03MB2356.namprd03.prod.outlook.com (10.166.74.151) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.77.7; Fri, 22 Sep 2017 07:42:53 +0000", "from BY2FFO11OLC007.protection.gbl (2a01:111:f400:7c0c::122) by\n\tDM5PR03CA0040.outlook.office365.com (2603:10b6:4:3b::29) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.56.9 via Frontend Transport; Fri, 22 Sep 2017 07:42:53 +0000", "from tx30smr01.am.freescale.net (192.88.168.50) by\n\tBY2FFO11OLC007.mail.protection.outlook.com (10.1.14.254) with\n\tMicrosoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.20.35.14\n\tvia Frontend Transport; Fri, 22 Sep 2017 07:42:52 +0000", "from titan.ap.freescale.net ([10.192.208.233])\n\tby tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id\n\tv8M7gidS030488; Fri, 22 Sep 2017 00:42:49 -0700" ], "Received-SPF": "Fail (protection.outlook.com: domain of nxp.com does not\n\tdesignate 192.88.168.50 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=192.88.168.50; helo=tx30smr01.am.freescale.net;", "From": "Zhiqiang Hou <Zhiqiang.Hou@nxp.com>", "To": "<linux-kernel@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>,\n\t<linux-pci@vger.kernel.org>, <bhelgaas@google.com>,\n\t<roy.zang@nxp.com>, <mingkai.hu@nxp.com>, <minghuan.lian@nxp.com>", "CC": "Hou Zhiqiang <Zhiqiang.Hou@nxp.com>", "Subject": "[PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode", "Date": "Fri, 22 Sep 2017 15:25:21 +0800", "Message-ID": "<20170922072522.36306-2-Zhiqiang.Hou@nxp.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170922072522.36306-1-Zhiqiang.Hou@nxp.com>", "References": "<20170922072522.36306-1-Zhiqiang.Hou@nxp.com>", "X-EOPAttributedMessage": "0", "X-Matching-Connectors": "131505397732009251;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:BN3PR03MB2356; ", "X-Forefront-PRVS": "0438F90F17", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "22 Sep 2017 07:42:52.9981\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "5afe0b00-7697-4969-b663-5eab37d5f47e", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN3PR03MB2356", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n\nThe Freescale PCIe controller advertises the MSI/MSI-X capability\nin both RC and Endpoint mode, but in RC mode it doesn't support\nMSI/MSI-X by it self, it can only transfer MSI/MSI-X from downstream\ndevices. So add this quirk to prevent use of MSI/MSI-X in RC mode.\n\nSigned-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n---\n drivers/pci/quirks.c | 8 ++++++++\n 1 file changed, 8 insertions(+)", "diff": "diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\nindex a4d33619a7bb..c1063a420f0c 100644\n--- a/drivers/pci/quirks.c\n+++ b/drivers/pci/quirks.c\n@@ -4799,3 +4799,11 @@ static void quirk_no_ats(struct pci_dev *pdev)\n /* AMD Stoney platform GPU */\n DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);\n #endif /* CONFIG_PCI_ATS */\n+\n+/* Freescale PCIe doesn't support MSI in RC mode */\n+static void quirk_fsl_no_msi(struct pci_dev *pdev)\n+{\n+\tif (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)\n+\t\tpdev->no_msi = 1;\n+}\n+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);\n", "prefixes": [ "1/2" ] }