[{"id":1784905,"web_url":"http://patchwork.ozlabs.org/comment/1784905/","msgid":"<20171011193737.GP25517@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-10-11T19:37:37","subject":"Re: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Fri, Sep 22, 2017 at 03:25:21PM +0800, Zhiqiang Hou wrote:\n> From: Hou Zhiqiang \n> \n> The Freescale PCIe controller advertises the MSI/MSI-X capability\n> in both RC and Endpoint mode, but in RC mode it doesn't support\n> MSI/MSI-X by it self, it can only transfer MSI/MSI-X from downstream\n\ns/it self,/itself;/\n\n> devices. So add this quirk to prevent use of MSI/MSI-X in RC mode.\n> \n> Signed-off-by: Hou Zhiqiang \n> ---\n> drivers/pci/quirks.c | 8 ++++++++\n> 1 file changed, 8 insertions(+)\n> \n> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\n> index a4d33619a7bb..c1063a420f0c 100644\n> --- a/drivers/pci/quirks.c\n> +++ b/drivers/pci/quirks.c\n> @@ -4799,3 +4799,11 @@ static void quirk_no_ats(struct pci_dev *pdev)\n> /* AMD Stoney platform GPU */\n> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);\n> #endif /* CONFIG_PCI_ATS */\n> +\n> +/* Freescale PCIe doesn't support MSI in RC mode */\n> +static void quirk_fsl_no_msi(struct pci_dev *pdev)\n> +{\n> +\tif (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)\n> +\t\tpdev->no_msi = 1;\n> +}\n> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);\n\nThis disables MSI for all Freescale root ports, past, present, and\nfuture. Is that really what you want? This is a bug (the root port\nshouldn't advertise MSI if it doesn't support it), and presumably it\nmight be fixed in some future device?\n\nThis needs an ack from Minghuan or Mingkai (based on MAINTAINERS).\n\nBjorn","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yC4524PTQz9t2V\n\tfor ;\n\tThu, 12 Oct 2017 06:37:42 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752486AbdJKThk (ORCPT );\n\tWed, 11 Oct 2017 15:37:40 -0400","from mail.kernel.org ([198.145.29.99]:40620 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1752451AbdJKThk (ORCPT );\n\tWed, 11 Oct 2017 15:37:40 -0400","from localhost (unknown [69.71.4.159])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 3C34D21483;\n\tWed, 11 Oct 2017 19:37:39 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 3C34D21483","Date":"Wed, 11 Oct 2017 14:37:37 -0500","From":"Bjorn Helgaas ","To":"Zhiqiang Hou ","Cc":"linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-pci@vger.kernel.org, bhelgaas@google.com, roy.zang@nxp.com,\n\tmingkai.hu@nxp.com, minghuan.lian@nxp.com","Subject":"Re: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","Message-ID":"<20171011193737.GP25517@bhelgaas-glaptop.roam.corp.google.com>","References":"<20170922072522.36306-1-Zhiqiang.Hou@nxp.com>\n\t<20170922072522.36306-2-Zhiqiang.Hou@nxp.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170922072522.36306-2-Zhiqiang.Hou@nxp.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1785108,"web_url":"http://patchwork.ozlabs.org/comment/1785108/","msgid":"","list_archive_url":null,"date":"2017-10-12T03:01:19","subject":"RE: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","submitter":{"id":68016,"url":"http://patchwork.ozlabs.org/api/people/68016/","name":"M.h. Lian","email":"Minghuan.Lian@nxp.com"},"content":"Hi Bjorn,\n\nThanks for your review.\nYes. All the freescale's PCIe controllers do not support to generate MSI interrupt.\nThe PCIe controllers developed for the next generation SoC do not support it either.\n\nAcked-by: Minghuan Lian \n\n> -----Original Message-----\n> From: Bjorn Helgaas [mailto:helgaas@kernel.org]\n> Sent: Thursday, October 12, 2017 3:38 AM\n> To: Z.q. Hou \n> Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-\n> pci@vger.kernel.org; bhelgaas@google.com; Roy Zang ;\n> Mingkai Hu ; M.h. Lian \n> Subject: Re: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode\n> \n> On Fri, Sep 22, 2017 at 03:25:21PM +0800, Zhiqiang Hou wrote:\n> > From: Hou Zhiqiang \n> >\n> > The Freescale PCIe controller advertises the MSI/MSI-X capability in\n> > both RC and Endpoint mode, but in RC mode it doesn't support MSI/MSI-X\n> > by it self, it can only transfer MSI/MSI-X from downstream\n> \n> s/it self,/itself;/\n> \n> > devices. So add this quirk to prevent use of MSI/MSI-X in RC mode.\n> >\n> > Signed-off-by: Hou Zhiqiang \n> > ---\n> > drivers/pci/quirks.c | 8 ++++++++\n> > 1 file changed, 8 insertions(+)\n> >\n> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index\n> > a4d33619a7bb..c1063a420f0c 100644\n> > --- a/drivers/pci/quirks.c\n> > +++ b/drivers/pci/quirks.c\n> > @@ -4799,3 +4799,11 @@ static void quirk_no_ats(struct pci_dev *pdev)\n> > /* AMD Stoney platform GPU */\n> > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);\n> > #endif /* CONFIG_PCI_ATS */\n> > +\n> > +/* Freescale PCIe doesn't support MSI in RC mode */ static void\n> > +quirk_fsl_no_msi(struct pci_dev *pdev) {\n> > +\tif (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)\n> > +\t\tpdev->no_msi = 1;\n> > +}\n> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,\n> > +quirk_fsl_no_msi);\n> \n> This disables MSI for all Freescale root ports, past, present, and future. Is that\n> really what you want? This is a bug (the root port shouldn't advertise MSI if it\n> doesn't support it), and presumably it might be fixed in some future device?\n> \n> This needs an ack from Minghuan or Mingkai (based on MAINTAINERS).\n> \n> Bjorn","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"wAAwLce0\";\n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=minghuan.lian@nxp.com; "],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yCFx26Rbhz9sBd\n\tfor ;\n\tThu, 12 Oct 2017 14:01:26 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752540AbdJLDBY (ORCPT );\n\tWed, 11 Oct 2017 23:01:24 -0400","from mail-eopbgr10045.outbound.protection.outlook.com\n\t([40.107.1.45]:11096\n\t\"EHLO EUR02-HE1-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1752337AbdJLDBX (ORCPT );\n\tWed, 11 Oct 2017 23:01:23 -0400","from VI1PR04MB1615.eurprd04.prod.outlook.com (10.164.84.149) by\n\tVI1PR04MB3088.eurprd04.prod.outlook.com (10.170.229.10) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.77.7; Thu, 12 Oct 2017 03:01:20 +0000","from VI1PR04MB1615.eurprd04.prod.outlook.com\n\t([fe80::a974:309e:c04:2ec7]) by\n\tVI1PR04MB1615.eurprd04.prod.outlook.com\n\t([fe80::a974:309e:c04:2ec7%13]) with mapi id 15.20.0077.020;\n\tThu, 12 Oct 2017 03:01:19 +0000"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=kCfiuY/fnEZ7uconod5CXkMK2RszxyL9fda+2XNXeFM=;\n\tb=wAAwLce05K044jGO3gEL6Q6fKpxwpTJLvUPPdaj1eSn9QBibCpkuGQBCxHUUa0307564jQi9Jy3pKC0pbCiLShG1fGtHdLjgXLKazhAgvRASqghICc6S9gciUuDZje3EUN1Vw90MpMuTPmUURSUnKv87i2jIkjNs/D6Drn5TQV0=","From":"\"M.h. Lian\" ","To":"Bjorn Helgaas , \"Z.q. Hou\" ","CC":"\"linux-kernel@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-pci@vger.kernel.org\" ,\n\t\"bhelgaas@google.com\" ,\n\t\"Roy Zang\" , Mingkai Hu ","Subject":"RE: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","Thread-Topic":"[PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","Thread-Index":"AQHTM3Zo2+0/F1OX0k+TniS4lz+8BaLfKdyAgAB313A=","Date":"Thu, 12 Oct 2017 03:01:19 +0000","Message-ID":"","References":"<20170922072522.36306-1-Zhiqiang.Hou@nxp.com>\n\t<20170922072522.36306-2-Zhiqiang.Hou@nxp.com>\n\t<20171011193737.GP25517@bhelgaas-glaptop.roam.corp.google.com>","In-Reply-To":"<20171011193737.GP25517@bhelgaas-glaptop.roam.corp.google.com>","Accept-Language":"zh-CN, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","authentication-results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-originalarrivaltime":"12 Oct 2017 03:01:19.3106\n\t(UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"VI1PR04MB3088","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1785119,"web_url":"http://patchwork.ozlabs.org/comment/1785119/","msgid":"","list_archive_url":null,"date":"2017-10-12T03:17:57","subject":"RE: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","submitter":{"id":67929,"url":"http://patchwork.ozlabs.org/api/people/67929/","name":"Z.Q. Hou","email":"zhiqiang.hou@nxp.com"},"content":"Hi Bjorn,\r\n\r\nThanks a lot for your comments!\r\n\r\n> -----Original Message-----\r\n> From: Bjorn Helgaas [mailto:helgaas@kernel.org]\r\n> Sent: 2017年10月12日 3:38\r\n> To: Z.q. Hou \r\n> Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;\r\n> linux-pci@vger.kernel.org; bhelgaas@google.com; Roy Zang\r\n> ; Mingkai Hu ; M.h. Lian\r\n> \r\n> Subject: Re: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode\r\n> \r\n> On Fri, Sep 22, 2017 at 03:25:21PM +0800, Zhiqiang Hou wrote:\r\n> > From: Hou Zhiqiang \r\n> >\r\n> > The Freescale PCIe controller advertises the MSI/MSI-X capability in\r\n> > both RC and Endpoint mode, but in RC mode it doesn't support MSI/MSI-X\r\n> > by it self, it can only transfer MSI/MSI-X from downstream\r\n> \r\n> s/it self,/itself;/\r\n\r\nI'll fix this typo in next version.\r\n\r\n> > devices. So add this quirk to prevent use of MSI/MSI-X in RC mode.\r\n> >\r\n> > Signed-off-by: Hou Zhiqiang \r\n> > ---\r\n> > drivers/pci/quirks.c | 8 ++++++++\r\n> > 1 file changed, 8 insertions(+)\r\n> >\r\n> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index\r\n> > a4d33619a7bb..c1063a420f0c 100644\r\n> > --- a/drivers/pci/quirks.c\r\n> > +++ b/drivers/pci/quirks.c\r\n> > @@ -4799,3 +4799,11 @@ static void quirk_no_ats(struct pci_dev *pdev)\r\n> > /* AMD Stoney platform GPU */\r\n> > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);\r\n> > #endif /* CONFIG_PCI_ATS */\r\n> > +\r\n> > +/* Freescale PCIe doesn't support MSI in RC mode */ static void\r\n> > +quirk_fsl_no_msi(struct pci_dev *pdev) {\r\n> > +\tif (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)\r\n> > +\t\tpdev->no_msi = 1;\r\n> > +}\r\n> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,\r\n> > +quirk_fsl_no_msi);\r\n> \r\n> This disables MSI for all Freescale root ports, past, present, and future. Is\r\n> that really what you want? This is a bug (the root port shouldn't advertise\r\n> MSI if it doesn't support it), and presumably it might be fixed in some future\r\n> device?\r\n\r\nFor the past and present, there isn't Freescale root ports supporting MSI. If the future Freescale root port support MSI, I'll add a patch for it checking the PCI device ID to determine if apply the quirk.\r\nAnd it should be ok for the root ports without this bug.\r\n\r\n> \r\n> This needs an ack from Minghuan or Mingkai (based on MAINTAINERS).\r\n> \r\n\r\nThanks,\r\nZhiqiang","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"MzcN/EZX\";\n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=zhiqiang.hou@nxp.com; "],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yCGJD2bskz9t2W\n\tfor ;\n\tThu, 12 Oct 2017 14:18:04 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752636AbdJLDSB (ORCPT );\n\tWed, 11 Oct 2017 23:18:01 -0400","from mail-db5eur01on0064.outbound.protection.outlook.com\n\t([104.47.2.64]:63712\n\t\"EHLO EUR01-DB5-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1752836AbdJLDSA (ORCPT );\n\tWed, 11 Oct 2017 23:18:00 -0400","from AM5PR0402MB2771.eurprd04.prod.outlook.com (10.175.41.13) by\n\tAM4PR04MB1601.eurprd04.prod.outlook.com (10.164.78.147) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.77.7; Thu, 12 Oct 2017 03:17:57 +0000","from AM5PR0402MB2771.eurprd04.prod.outlook.com\n\t([fe80::1ea:d5af:e18e:3b65]) by\n\tAM5PR0402MB2771.eurprd04.prod.outlook.com\n\t([fe80::1ea:d5af:e18e:3b65%13]) with mapi id 15.20.0077.020;\n\tThu, 12 Oct 2017 03:17:57 +0000"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=NVIHV+XO6V2snbcpiCOQmVZsDPxP6CqAN+Mmy8i24EI=;\n\tb=MzcN/EZXwMFYpasmeJ3Ho8EZh5/sQf1nD0M07X+kxeGpW8nOlJ1Sem0RF55fPjtrzsLxdtNEf3cmaMx0HivbShOnjQq2jVc1kRIHiLqjkLwF2AzRwqWWtDpyRjaEI7Xfi/+kc8BhjRynyR2VSXcHWa5fgzrRbkVyKM52P01JMnw=","From":"\"Z.q. Hou\" ","To":"Bjorn Helgaas ","CC":"\"linux-kernel@vger.kernel.org\" ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-pci@vger.kernel.org\" ,\n\t\"bhelgaas@google.com\" ,\n\t\"Roy Zang\" , Mingkai Hu ,\n\t\"M.h. Lian\" ","Subject":"RE: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","Thread-Topic":"[PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","Thread-Index":"AQHTM3ZowioOzRa4+k2itj8tgleitqLfKdyAgAB6toA=","Date":"Thu, 12 Oct 2017 03:17:57 +0000","Message-ID":"","References":"<20170922072522.36306-1-Zhiqiang.Hou@nxp.com>\n\t<20170922072522.36306-2-Zhiqiang.Hou@nxp.com>\n\t<20171011193737.GP25517@bhelgaas-glaptop.roam.corp.google.com>","In-Reply-To":"<20171011193737.GP25517@bhelgaas-glaptop.roam.corp.google.com>","Accept-Language":"zh-CN, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","authentication-results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"MzcN/EZX\";\n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=zhiqiang.hou@nxp.com; "],"x-originating-ip":"[199.59.231.64]","x-ms-publictraffictype":"Email","x-microsoft-exchange-diagnostics":"1; AM4PR04MB1601;\n\t6:KKhXeDrb546yazH+gY0jNn8c9A16psNgDIIqyl4PzD3/3Vr6wMUGsx+H+RkG7GzbfSgK/7pMDJ3ECNFJd2SL06Bc1dRjGSTxm7T3ofb8zwkJ7xhZOMc9L5/QAmSTX7R/sde4sSQnoAtWi20JWr9fI7cHT5xdp20/8JIWo340Fh41QhdWcbKLO4O5G41WSHVNcwZQTHJ9HKdS9MWyfDZHjAz7BHwDeFF1A8qXdvW3vM0q/UBO6rt58K2eQaypaB02Rr5Pq5R70j0dHpceZeKYI9X/9xA9tZsncmnIM7oW4+YcuoEL7Z2xnVa4SOdo0FAzyrGlSuDcPXjb7R/HJwleXg==;\n\t5:Qtl6oWnjGCh5hIpW+fsu9e5+/yZUZNYll16yH4wg2nnpwzi4zuTDQrGxLomb1Uhs4KgnoCrDoCfMLINECfC3sagpP/GDPp2w1NOrg4VT9sVxpbzOYXg0EeYfS4+DqUcq0SgpOlAWac92qiO4dmsrsg==;\n\t24:0fhIw3QnrILBQqGr+hmPJddjUyUL6DGph06gTATjaEci2nqV3H66hVZpxFoQ6uDS64AT5zadowNvICEBSmXb4cGRBvSLbPDsRk2sBEvaqaQ=;\n\t7:RL1ecL18/AK5vXrXZG0N+KjjsOqfPqzEmtvkeDgWnKnTNQnCwFXV20bWOx828ET1hxsFPKa8rZ87nbTWh9moOtYVjhKgNon8FNI7cky+nlLiYaI1mYBzq95YDs/9nqP3UPcp1HAon8JvWNb1jY+qrTUdRz2u2mgGzDxDa706KEYkSIxcxxtbNTEH7AhHawboMrzLtZdGCGuN5rN0s/pCb+omUPXw5qGIfxERuNwPxe4=","x-ms-exchange-antispam-srfa-diagnostics":"SSOS;SSOR;","x-forefront-antispam-report":"SFV:SKI; SCL:-1; SFV:NSPM;\n\tSFS:(10009020)(6009001)(39860400002)(376002)(346002)(199003)(189002)(24454002)(13464003)(7696004)(9686003)(54906003)(3280700002)(106356001)(3660700001)(76176999)(4326008)(105586002)(101416001)(68736007)(54356999)(99286003)(229853002)(6916009)(316002)(53546010)(81166006)(81156014)(66066001)(575784001)(8936002)(33656002)(25786009)(8676002)(6116002)(5250100002)(2900100001)(97736004)(6506006)(50986999)(3846002)(53936002)(14454004)(102836003)(7736002)(6246003)(55016002)(5660300001)(74316002)(478600001)(305945005)(86362001)(2906002)(189998001)(2950100002)(6436002)(34040400001);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:AM4PR04MB1601;\n\tH:AM5PR0402MB2771.eurprd04.prod.outlook.com; FPR:; SPF:None;\n\tPTR:InfoNoRecords; A:1; MX:1; LANG:en; ","x-ms-office365-filtering-correlation-id":"0a62d3d3-ea6b-4be5-28fa-08d5111fd5d3","x-ms-office365-filtering-ht":"Tenant","x-microsoft-antispam":"UriScan:; BCL:0; PCL:0;\n\tRULEID:(22001)(2017030254152)(48565401081)(2017052603199)(201703131423075)(201703031133081)(201702281549075);\n\tSRVR:AM4PR04MB1601; ","x-ms-traffictypediagnostic":"AM4PR04MB1601:","x-exchange-antispam-report-test":"UriScan:(9452136761055)(185117386973197)(258649278758335)(211936372134217);","x-microsoft-antispam-prvs":"","x-exchange-antispam-report-cfa-test":"BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(2401047)(8121501046)(5005006)(3002001)(93006095)(93001095)(100000703101)(100105400095)(10201501046)(920507026)(6055026)(6041248)(20161123562025)(20161123558100)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123560025)(20161123555025)(20161123564025)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:AM4PR04MB1601; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:AM4PR04MB1601; ","x-forefront-prvs":"04583CED1A","received-spf":"None (protection.outlook.com: nxp.com does not designate\n\tpermitted sender hosts)","spamdiagnosticoutput":"1:99","spamdiagnosticmetadata":"NSPM","Content-Type":"text/plain; charset=\"gb2312\"","Content-Transfer-Encoding":"base64","MIME-Version":"1.0","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-originalarrivaltime":"12 Oct 2017 03:17:57.0743\n\t(UTC)","X-MS-Exchange-CrossTenant-fromentityheader":"Hosted","X-MS-Exchange-CrossTenant-id":"686ea1d3-bc2b-4c6f-a92c-d99c5c301635","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"AM4PR04MB1601","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}}]