Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/817031/?format=api
{ "id": 817031, "url": "http://patchwork.ozlabs.org/api/patches/817031/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170921164940.20343-5-georgi.djakov@linaro.org/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170921164940.20343-5-georgi.djakov@linaro.org>", "list_archive_url": null, "date": "2017-09-21T16:49:37", "name": "[v9,4/7] clk: qcom: Add A53 PLL support", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "358966758c0eadfb4f5548502dd2de6bcda2bbb5", "submitter": { "id": 70295, "url": "http://patchwork.ozlabs.org/api/people/70295/?format=api", "name": "Georgi Djakov", "email": "georgi.djakov@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170921164940.20343-5-georgi.djakov@linaro.org/mbox/", "series": [ { "id": 4442, "url": "http://patchwork.ozlabs.org/api/series/4442/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4442", "date": "2017-09-21T16:49:33", "name": "Add support for Qualcomm A53 CPU clock", "version": 9, "mbox": "http://patchwork.ozlabs.org/series/4442/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817031/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817031/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"T74in/PE\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyjLZ1hzgz9t3C\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 02:51:34 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751745AbdIUQvc (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tThu, 21 Sep 2017 12:51:32 -0400", "from mail-wm0-f47.google.com ([74.125.82.47]:50182 \"EHLO\n\tmail-wm0-f47.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751870AbdIUQtu (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Thu, 21 Sep 2017 12:49:50 -0400", "by mail-wm0-f47.google.com with SMTP id b195so3559859wmb.5\n\tfor <devicetree@vger.kernel.org>;\n\tThu, 21 Sep 2017 09:49:49 -0700 (PDT)", "from mms-0441.qualcomm.mm-sol.com ([212.45.67.2])\n\tby smtp.googlemail.com with ESMTPSA id\n\ti16sm993311edj.29.2017.09.21.09.49.46\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tThu, 21 Sep 2017 09:49:47 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=PwwBcdzRnJVhmA9Fo2vN/PO33kPNYzKtlUlIy+FKAx8=;\n\tb=T74in/PEHnYvT/jnUkToaOXxqWxnjsjUO0UIHnZI8zHFc4iTBHztH9y+CDhsu7qXiT\n\tS595C2wjft81M+0WofTQdWJQNGhvDBVICk2uvDrmEs56iwYL3Uy4Ws5AIj9XLxMeu4rP\n\teFb1O62t+uCam/jVFR8qC8LjEZ5Wnnv1dxs8E=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=PwwBcdzRnJVhmA9Fo2vN/PO33kPNYzKtlUlIy+FKAx8=;\n\tb=UWhKt6cgcIYc6CPWs43HY+WmfUt43rE1eP06+lRTpJkQnSdGFZTOfco/flAL1pY00v\n\tBqb25GugWe90qId8zn7V6Z/jixgVS0nr11EhAfev/X3+rUMAZ+wIpSDzxZiA++6b24gi\n\tw4m7TYtq6Ilo1gSu3Da8gU2XPyEqeI4J4p+A6XlLjMwjED/EtUTLD6fGqB0t5Hwg94lH\n\twGH3rro24dr/F3rfov7CWqIuI7bAP6OhreHmb8Fx+q4jc5xnLgP/9cy3xQ+VpaC9jltS\n\twfn1qkH7wXmu/nr1bE7N89jdwdLran5qhgAdzRXYIsET15kHcYrO3nMVWFcZeHIQhdph\n\tLT/w==", "X-Gm-Message-State": "AHPjjUjAio7lE8vRc8TW71tZRgvN9486OchktK2HBCi+L3/Ii7T/8NfZ\n\tqXd2SfJm4lOFwWNrj1AADzicZ2f093w=", "X-Google-Smtp-Source": "AOwi7QClC9Po6MEghA/9E9GRI++LgJ67tCWa+LsIGTAAgEEnfm2en5SNb5I6cIz5ZiJ7wwKs7NJtsA==", "X-Received": "by 10.80.224.79 with SMTP id g15mr1845079edl.259.1506012588584; \n\tThu, 21 Sep 2017 09:49:48 -0700 (PDT)", "From": "Georgi Djakov <georgi.djakov@linaro.org>", "To": "sboyd@codeaurora.org, jassisinghbrar@gmail.com,\n\tbjorn.andersson@linaro.org, robh+dt@kernel.org", "Cc": "mturquette@baylibre.com, linux-clk@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n\tdevicetree@vger.kernel.org, georgi.djakov@linaro.org", "Subject": "[PATCH v9 4/7] clk: qcom: Add A53 PLL support", "Date": "Thu, 21 Sep 2017 19:49:37 +0300", "Message-Id": "<20170921164940.20343-5-georgi.djakov@linaro.org>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170921164940.20343-1-georgi.djakov@linaro.org>", "References": "<20170921164940.20343-1-georgi.djakov@linaro.org>", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs,\na primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources\nare connected to a mux and half-integer divider, which is feeding the\nCPU cores.\n\nThis patch adds support for the primary CPU PLL which generates the\nhigher range of frequencies above 1GHz.\n\nSigned-off-by: Georgi Djakov <georgi.djakov@linaro.org>\n---\n .../devicetree/bindings/clock/qcom,a53pll.txt | 22 +++++\n drivers/clk/qcom/Kconfig | 10 ++\n drivers/clk/qcom/Makefile | 1 +\n drivers/clk/qcom/a53-pll.c | 107 +++++++++++++++++++++\n 4 files changed, 140 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53pll.txt\n create mode 100644 drivers/clk/qcom/a53-pll.c\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html", "diff": "diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.txt b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt\nnew file mode 100644\nindex 000000000000..e3fa8118eaee\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.txt\n@@ -0,0 +1,22 @@\n+Qualcomm MSM8916 A53 PLL Binding\n+--------------------------------\n+The A53 PLL on MSM8916 platforms is the main CPU PLL used used for frequencies\n+above 1GHz.\n+\n+Required properties :\n+- compatible : Shall contain only one of the following:\n+\n+\t\t\"qcom,msm8916-a53pll\"\n+\n+- reg : shall contain base register location and length\n+\n+- #clock-cells : must be set to <0>\n+\n+Example:\n+\n+\ta53pll: clock@b016000 {\n+\t\tcompatible = \"qcom,msm8916-a53pll\";\n+\t\treg = <0xb016000 0x40>;\n+\t\t#clock-cells = <0>;\n+\t};\n+\ndiff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig\nindex 9f6c278deead..81ac7b9378fe 100644\n--- a/drivers/clk/qcom/Kconfig\n+++ b/drivers/clk/qcom/Kconfig\n@@ -12,6 +12,16 @@ config COMMON_CLK_QCOM\n \tselect REGMAP_MMIO\n \tselect RESET_CONTROLLER\n \n+config QCOM_A53PLL\n+\tbool \"MSM8916 A53 PLL\"\n+\tdepends on COMMON_CLK_QCOM\n+\tdefault ARCH_QCOM\n+\thelp\n+\t Support for the A53 PLL on MSM8916 devices. It provides\n+\t the CPU with frequencies above 1GHz.\n+\t Say Y if you want to support higher CPU frequencies on MSM8916\n+\t devices.\n+\n config QCOM_CLK_RPM\n \ttristate \"RPM based Clock Controller\"\n \tdepends on COMMON_CLK_QCOM && MFD_QCOM_RPM\ndiff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile\nindex 3f3aff229fb7..19ae884b5166 100644\n--- a/drivers/clk/qcom/Makefile\n+++ b/drivers/clk/qcom/Makefile\n@@ -31,5 +31,6 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o\n obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o\n obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o\n obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o\n+obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o\n obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o\n obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o\ndiff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c\nnew file mode 100644\nindex 000000000000..6276934daa0a\n--- /dev/null\n+++ b/drivers/clk/qcom/a53-pll.c\n@@ -0,0 +1,107 @@\n+/*\n+ * Copyright (c) 2017, Linaro Limited\n+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 and\n+ * only version 2 as published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ */\n+\n+#include <linux/clk-provider.h>\n+#include <linux/kernel.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+\n+#include \"clk-pll.h\"\n+#include \"clk-regmap.h\"\n+\n+static const struct pll_freq_tbl a53pll_freq[] = {\n+\t{ 998400000, 52, 0x0, 0x1, 0 },\n+\t{ 1094400000, 57, 0x0, 0x1, 0 },\n+\t{ 1152000000, 62, 0x0, 0x1, 0 },\n+\t{ 1209600000, 65, 0x0, 0x1, 0 },\n+\t{ 1401600000, 73, 0x0, 0x1, 0 },\n+};\n+\n+static const struct regmap_config a53pll_regmap_config = {\n+\t.reg_bits\t\t= 32,\n+\t.reg_stride\t\t= 4,\n+\t.val_bits\t\t= 32,\n+\t.max_register\t\t= 0x40,\n+\t.fast_io\t\t= true,\n+};\n+\n+static const struct of_device_id qcom_a53pll_match_table[] = {\n+\t{ .compatible = \"qcom,msm8916-a53pll\" },\n+\t{ }\n+};\n+\n+static int qcom_a53pll_probe(struct platform_device *pdev)\n+{\n+\tstruct device *dev = &pdev->dev;\n+\tstruct regmap *regmap;\n+\tstruct resource *res;\n+\tstruct clk_pll *pll;\n+\tvoid __iomem *base;\n+\tstruct clk_init_data init = { };\n+\tint ret;\n+\n+\tpll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);\n+\tif (!pll)\n+\t\treturn -ENOMEM;\n+\n+\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n+\tbase = devm_ioremap_resource(dev, res);\n+\tif (IS_ERR(base))\n+\t\treturn PTR_ERR(base);\n+\n+\tregmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config);\n+\tif (IS_ERR(regmap))\n+\t\treturn PTR_ERR(regmap);\n+\n+\tpll->l_reg = 0x04;\n+\tpll->m_reg = 0x08;\n+\tpll->n_reg = 0x0c;\n+\tpll->config_reg = 0x14;\n+\tpll->mode_reg = 0x00;\n+\tpll->status_reg = 0x1c;\n+\tpll->status_bit = 16;\n+\tpll->freq_tbl = a53pll_freq;\n+\n+\tinit.name = \"a53pll\";\n+\tinit.parent_names = (const char *[]){ \"xo\" };\n+\tinit.num_parents = 1;\n+\tinit.ops = &clk_pll_sr2_ops;\n+\tinit.flags = CLK_IS_CRITICAL;\n+\tpll->clkr.hw.init = &init;\n+\n+\tret = devm_clk_register_regmap(dev, &pll->clkr);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to register regmap clock: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,\n+\t\t\t\t &pll->clkr.hw);\n+\tif (ret) {\n+\t\tdev_err(dev, \"failed to add clock provider: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static struct platform_driver qcom_a53pll_driver = {\n+\t.probe = qcom_a53pll_probe,\n+\t.driver = {\n+\t\t.name = \"qcom-a53pll\",\n+\t\t.of_match_table = qcom_a53pll_match_table,\n+\t},\n+};\n+\n+builtin_platform_driver(qcom_a53pll_driver);\n", "prefixes": [ "v9", "4/7" ] }