[{"id":1773158,"web_url":"http://patchwork.ozlabs.org/comment/1773158/","msgid":"<20170921225125.f4dhxsodfgq5rrdt@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-21T22:51:25","subject":"Re: [PATCH v9 4/7] clk: qcom: Add A53 PLL support","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Thu, Sep 21, 2017 at 07:49:37PM +0300, Georgi Djakov wrote:\n> The CPUs on Qualcomm MSM8916-based platforms are clocked by two PLLs,\n> a primary (A53) CPU PLL and a secondary fixed-rate GPLL0. These sources\n> are connected to a mux and half-integer divider, which is feeding the\n> CPU cores.\n> \n> This patch adds support for the primary CPU PLL which generates the\n> higher range of frequencies above 1GHz.\n> \n> Signed-off-by: Georgi Djakov \n> ---\n> .../devicetree/bindings/clock/qcom,a53pll.txt | 22 +++++\n\nPlease add acks when posting new versions.\n\n> drivers/clk/qcom/Kconfig | 10 ++\n> drivers/clk/qcom/Makefile | 1 +\n> drivers/clk/qcom/a53-pll.c | 107 +++++++++++++++++++++\n> 4 files changed, 140 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/clock/qcom,a53pll.txt\n> create mode 100644 drivers/clk/qcom/a53-pll.c\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xysL71HPSz9sxR\n\tfor ;\n\tFri, 22 Sep 2017 08:51:43 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751823AbdIUWv2 (ORCPT\n\t);\n\tThu, 21 Sep 2017 18:51:28 -0400","from mail-pg0-f66.google.com ([74.125.83.66]:32828 \"EHLO\n\tmail-pg0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751728AbdIUWv1 (ORCPT\n\t); Thu, 21 Sep 2017 18:51:27 -0400","by mail-pg0-f66.google.com with SMTP id i130so4179162pgc.0;\n\tThu, 21 Sep 2017 15:51:27 -0700 (PDT)","from localhost ([2620:0:1000:fd28:e83d:5428:912b:b325])\n\tby smtp.gmail.com with ESMTPSA id\n\tj9sm4632392pgc.11.2017.09.21.15.51.25\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tThu, 21 Sep 2017 15:51:25 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170921164940.20343-5-georgi.djakov@linaro.org>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1794016,"web_url":"http://patchwork.ozlabs.org/comment/1794016/","msgid":"<20171026041923.GK1575@tuxbook>","list_archive_url":null,"date":"2017-10-26T04:19:23","subject":"Re: [PATCH v9 4/7] clk: qcom: Add A53 PLL support","submitter":{"id":68398,"url":"http://patchwork.ozlabs.org/api/people/68398/","name":"Bjorn Andersson","email":"bjorn.andersson@linaro.org"},"content":"On Thu 21 Sep 09:49 PDT 2017, Georgi Djakov wrote:\n> diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c\n[..]\n> +\n> +static const struct of_device_id qcom_a53pll_match_table[] = {\n> +\t{ .compatible = \"qcom,msm8916-a53pll\" },\n> +\t{ }\n> +};\n\nMove the match table below the probe.\n\n> +\n> +static int qcom_a53pll_probe(struct platform_device *pdev)\n> +{\n> +\tstruct device *dev = &pdev->dev;\n> +\tstruct regmap *regmap;\n> +\tstruct resource *res;\n> +\tstruct clk_pll *pll;\n> +\tvoid __iomem *base;\n> +\tstruct clk_init_data init = { };\n> +\tint ret;\n> +\n> +\tpll = devm_kzalloc(dev, sizeof(*pll), GFP_KERNEL);\n> +\tif (!pll)\n> +\t\treturn -ENOMEM;\n> +\n> +\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n> +\tbase = devm_ioremap_resource(dev, res);\n> +\tif (IS_ERR(base))\n> +\t\treturn PTR_ERR(base);\n> +\n> +\tregmap = devm_regmap_init_mmio(dev, base, &a53pll_regmap_config);\n> +\tif (IS_ERR(regmap))\n> +\t\treturn PTR_ERR(regmap);\n> +\n> +\tpll->l_reg = 0x04;\n> +\tpll->m_reg = 0x08;\n> +\tpll->n_reg = 0x0c;\n> +\tpll->config_reg = 0x14;\n> +\tpll->mode_reg = 0x00;\n> +\tpll->status_reg = 0x1c;\n> +\tpll->status_bit = 16;\n> +\tpll->freq_tbl = a53pll_freq;\n> +\n> +\tinit.name = \"a53pll\";\n> +\tinit.parent_names = (const char *[]){ \"xo\" };\n> +\tinit.num_parents = 1;\n> +\tinit.ops = &clk_pll_sr2_ops;\n> +\tinit.flags = CLK_IS_CRITICAL;\n> +\tpll->clkr.hw.init = &init;\n> +\n> +\tret = devm_clk_register_regmap(dev, &pll->clkr);\n> +\tif (ret) {\n> +\t\tdev_err(dev, \"failed to register regmap clock: %d\\n\", ret);\n> +\t\treturn ret;\n> +\t}\n> +\n> +\tret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,\n> +\t\t\t\t &pll->clkr.hw);\n> +\tif (ret) {\n> +\t\tdev_err(dev, \"failed to add clock provider: %d\\n\", ret);\n> +\t\treturn ret;\n> +\t}\n> +\n> +\treturn 0;\n> +}\n> +\n> +static struct platform_driver qcom_a53pll_driver = {\n> +\t.probe = qcom_a53pll_probe,\n\nI think you should either have a remove here that\nof_clk_del_hw_provider() or set suppress_bind_attrs in the .driver.\n\n> +\t.driver = {\n> +\t\t.name = \"qcom-a53pll\",\n> +\t\t.of_match_table = qcom_a53pll_match_table,\n> +\t},\n> +};\n> +\n> +builtin_platform_driver(qcom_a53pll_driver);\n\nOther than these nits I think this looks good.\n\nRegards,\nBjorn\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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