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GET /api/patches/817030/?format=api
{ "id": 817030, "url": "http://patchwork.ozlabs.org/api/patches/817030/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170921164940.20343-7-georgi.djakov@linaro.org/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170921164940.20343-7-georgi.djakov@linaro.org>", "list_archive_url": null, "date": "2017-09-21T16:49:39", "name": "[v9,6/7] dt-bindings: clock: Document qcom,apcs binding", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "6d1573f059cd3dc208fd4742988e3eedc559b4e8", "submitter": { "id": 70295, "url": "http://patchwork.ozlabs.org/api/people/70295/?format=api", "name": "Georgi Djakov", "email": "georgi.djakov@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170921164940.20343-7-georgi.djakov@linaro.org/mbox/", "series": [ { "id": 4442, "url": "http://patchwork.ozlabs.org/api/series/4442/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=4442", "date": "2017-09-21T16:49:33", "name": "Add support for Qualcomm A53 CPU clock", "version": 9, "mbox": "http://patchwork.ozlabs.org/series/4442/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/817030/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/817030/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"b0Zcf9RD\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyjLK4WL4z9t3C\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tFri, 22 Sep 2017 02:51:21 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751730AbdIUQvD (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tThu, 21 Sep 2017 12:51:03 -0400", "from mail-wm0-f53.google.com ([74.125.82.53]:50200 \"EHLO\n\tmail-wm0-f53.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751861AbdIUQtx (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Thu, 21 Sep 2017 12:49:53 -0400", "by mail-wm0-f53.google.com with SMTP id b195so3560221wmb.5\n\tfor <devicetree@vger.kernel.org>;\n\tThu, 21 Sep 2017 09:49:52 -0700 (PDT)", "from mms-0441.qualcomm.mm-sol.com ([212.45.67.2])\n\tby smtp.googlemail.com with ESMTPSA id\n\ti16sm993311edj.29.2017.09.21.09.49.50\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tThu, 21 Sep 2017 09:49:51 -0700 (PDT)" ], "DKIM-Signature": "v=1; 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\n\tThu, 21 Sep 2017 09:49:51 -0700 (PDT)", "From": "Georgi Djakov <georgi.djakov@linaro.org>", "To": "sboyd@codeaurora.org, jassisinghbrar@gmail.com,\n\tbjorn.andersson@linaro.org, robh+dt@kernel.org", "Cc": "mturquette@baylibre.com, linux-clk@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,\n\tdevicetree@vger.kernel.org, georgi.djakov@linaro.org", "Subject": "[PATCH v9 6/7] dt-bindings: clock: Document qcom,apcs binding", "Date": "Thu, 21 Sep 2017 19:49:39 +0300", "Message-Id": "<20170921164940.20343-7-georgi.djakov@linaro.org>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170921164940.20343-1-georgi.djakov@linaro.org>", "References": "<20170921164940.20343-1-georgi.djakov@linaro.org>", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "Add device-tree binding documentation for the Qualcom APCS clock\ncontroller. This clock controller is a mux and half-integer divider\nand provides the clock for the application CPU.\n\nSigned-off-by: Georgi Djakov <georgi.djakov@linaro.org>\n---\n .../devicetree/bindings/clock/qcom,apcs.txt | 27 ++++++++++++++++++++++\n 1 file changed, 27 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/clock/qcom,apcs.txt\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html", "diff": "diff --git a/Documentation/devicetree/bindings/clock/qcom,apcs.txt b/Documentation/devicetree/bindings/clock/qcom,apcs.txt\nnew file mode 100644\nindex 000000000000..8083bcc33ebe\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/clock/qcom,apcs.txt\n@@ -0,0 +1,27 @@\n+Qualcomm APCS Clock Controller Binding\n+--------------------------------------\n+The APCS hardware block provides a combined mux and half-integer divider\n+functionality. It is used for a main CPU clock mux on MSM8916 platforms.\n+\n+Required properties :\n+- compatible : shall contain only one of the following:\n+\n+\t\t\"qcom,msm8916-apcs-clk\"\n+\n+- clocks : shall be the phandle to the main input CPU PLL clock\n+\n+- #clock-cells : must be set to <0>\n+\n+Example:\n+\n+\tapcs: mailbox@b011000 {\n+\t\tcompatible = \"qcom,msm8916-apcs-kpss-global\";\n+\t\treg = <0xb011000 0x1000>;\n+\t\t#mbox-cells = <1>;\n+\n+\t\tapcs_clk: apcs_clk {\n+\t\t\tcompatible = \"qcom,msm8916-apcs-clk\";\n+\t\t\tclocks = <&a53pll>;\n+\t\t\t#clock-cells = <0>;\n+\t\t};\n+\t};\n", "prefixes": [ "v9", "6/7" ] }