[{"id":1779274,"web_url":"http://patchwork.ozlabs.org/comment/1779274/","msgid":"<20171003214107.4xvk5motoedpnjbr@rob-hp-laptop>","list_archive_url":null,"date":"2017-10-03T21:41:07","subject":"Re: [PATCH v9 6/7] dt-bindings: clock: Document qcom,apcs binding","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Thu, Sep 21, 2017 at 07:49:39PM +0300, Georgi Djakov wrote:\n> Add device-tree binding documentation for the Qualcom APCS clock\n> controller. This clock controller is a mux and half-integer divider\n> and provides the clock for the application CPU.\n> \n> Signed-off-by: Georgi Djakov \n> ---\n> .../devicetree/bindings/clock/qcom,apcs.txt | 27 ++++++++++++++++++++++\n> 1 file changed, 27 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/clock/qcom,apcs.txt\n> \n> diff --git a/Documentation/devicetree/bindings/clock/qcom,apcs.txt b/Documentation/devicetree/bindings/clock/qcom,apcs.txt\n> new file mode 100644\n> index 000000000000..8083bcc33ebe\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/clock/qcom,apcs.txt\n> @@ -0,0 +1,27 @@\n> +Qualcomm APCS Clock Controller Binding\n> +--------------------------------------\n> +The APCS hardware block provides a combined mux and half-integer divider\n> +functionality. It is used for a main CPU clock mux on MSM8916 platforms.\n> +\n> +Required properties :\n> +- compatible : shall contain only one of the following:\n> +\n> +\t\t\"qcom,msm8916-apcs-clk\"\n> +\n> +- clocks : shall be the phandle to the main input CPU PLL clock\n> +\n> +- #clock-cells : must be set to <0>\n> +\n> +Example:\n> +\n> +\tapcs: mailbox@b011000 {\n> +\t\tcompatible = \"qcom,msm8916-apcs-kpss-global\";\n> +\t\treg = <0xb011000 0x1000>;\n> +\t\t#mbox-cells = <1>;\n> +\n> +\t\tapcs_clk: apcs_clk {\n\nDon't use '_' in node names. This can be just \"clock\".\n\nOtherwise,\n\nAcked-by: Rob Herring \n\n> +\t\t\tcompatible = \"qcom,msm8916-apcs-clk\";\n> +\t\t\tclocks = <&a53pll>;\n> +\t\t\t#clock-cells = <0>;\n> +\t\t};\n> +\t};\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y6CCS4Sjwz9sPr\n\tfor ;\n\tWed, 4 Oct 2017 08:41:24 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751117AbdJCVlK (ORCPT\n\t);\n\tTue, 3 Oct 2017 17:41:10 -0400","from mail-oi0-f65.google.com ([209.85.218.65]:33921 \"EHLO\n\tmail-oi0-f65.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750841AbdJCVlJ (ORCPT\n\t); Tue, 3 Oct 2017 17:41:09 -0400","by mail-oi0-f65.google.com with SMTP id q133so3974360oic.1;\n\tTue, 03 Oct 2017 14:41:08 -0700 (PDT)","from localhost (216-188-254-6.dyn.grandenetworks.net.\n\t[216.188.254.6]) by smtp.gmail.com with ESMTPSA id\n\tq82sm1377255oih.32.2017.10.03.14.41.07\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 03 Oct 2017 14:41:07 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=/Dgh0jcar6HtXyZcGJ9FL86wVveSDE6mLwQK7HXpUHg=;\n\tb=LDKZ/DIAVOjFw4crVuiV8bc+b8lIJbyZJyYtAIp2Ffo+VbbvwbLlymSm4TqjwtyrbF\n\tWYSMGUeDqZ2LO2vDipvif/23sihz5vAcX0TzeaTUXyQVlsDc4xU2+lUj0BIKNHrnVoT3\n\t8nDcptWZCd9egljphuQSdSbrUFreuFyfnp1xG9DGZpeIn4gH9lduYx2iWDVcrVLpXavK\n\t1BCGRuPS5uAtFK8KxghP0F5gzIZl2L2J9lLP0ktP0rZ7LAd0H+S731OgBAqBDb9YJPx3\n\t6DzgCWgFhFx65IXzKpMkIwttdfP6Sf+SIwdzsOt574icoesEck9YMjxjrVujnNnX0WQm\n\txH1g==","X-Gm-Message-State":"AMCzsaWDaGa1XARjEhjLB7FBNv90SfqC8VXRTsLC5cCBVUS5QhE8z3vZ\n\tNGTCieear0svJ9vSQuyhdg==","X-Google-Smtp-Source":"AOwi7QDlYZQDztrTzNFpijNSDmzuWhUKEXUQHnGLfON/M9K5bd9DM7nI0Qy1n+V/NzJUN1gSZKrtzA==","X-Received":"by 10.157.27.147 with SMTP id z19mr10801445otd.462.1507066868266;\n\tTue, 03 Oct 2017 14:41:08 -0700 (PDT)","Date":"Tue, 3 Oct 2017 16:41:07 -0500","From":"Rob Herring ","To":"Georgi Djakov ","Cc":"sboyd@codeaurora.org, jassisinghbrar@gmail.com,\n\tbjorn.andersson@linaro.org, mturquette@baylibre.com,\n\tlinux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org","Subject":"Re: [PATCH v9 6/7] dt-bindings: clock: Document qcom,apcs binding","Message-ID":"<20171003214107.4xvk5motoedpnjbr@rob-hp-laptop>","References":"<20170921164940.20343-1-georgi.djakov@linaro.org>\n\t<20170921164940.20343-7-georgi.djakov@linaro.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170921164940.20343-7-georgi.djakov@linaro.org>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1794015,"web_url":"http://patchwork.ozlabs.org/comment/1794015/","msgid":"<20171026041326.GJ1575@tuxbook>","list_archive_url":null,"date":"2017-10-26T04:13:26","subject":"Re: [PATCH v9 6/7] dt-bindings: clock: Document qcom,apcs binding","submitter":{"id":68398,"url":"http://patchwork.ozlabs.org/api/people/68398/","name":"Bjorn Andersson","email":"bjorn.andersson@linaro.org"},"content":"On Thu 21 Sep 09:49 PDT 2017, Georgi Djakov wrote:\n\n> Add device-tree binding documentation for the Qualcom APCS clock\n> controller. This clock controller is a mux and half-integer divider\n> and provides the clock for the application CPU.\n> \n> Signed-off-by: Georgi Djakov \n> ---\n> .../devicetree/bindings/clock/qcom,apcs.txt | 27 ++++++++++++++++++++++\n> 1 file changed, 27 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/clock/qcom,apcs.txt\n> \n> diff --git a/Documentation/devicetree/bindings/clock/qcom,apcs.txt b/Documentation/devicetree/bindings/clock/qcom,apcs.txt\n> new file mode 100644\n> index 000000000000..8083bcc33ebe\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/clock/qcom,apcs.txt\n> @@ -0,0 +1,27 @@\n> +Qualcomm APCS Clock Controller Binding\n> +--------------------------------------\n> +The APCS hardware block provides a combined mux and half-integer divider\n> +functionality. It is used for a main CPU clock mux on MSM8916 platforms.\n> +\n> +Required properties :\n> +- compatible : shall contain only one of the following:\n> +\n> +\t\t\"qcom,msm8916-apcs-clk\"\n> +\n> +- clocks : shall be the phandle to the main input CPU PLL clock\n> +\n> +- #clock-cells : must be set to <0>\n> +\n> +Example:\n> +\n> +\tapcs: mailbox@b011000 {\n\nThis node describes the \"apcs kpss global\"-block.\n\n> +\t\tcompatible = \"qcom,msm8916-apcs-kpss-global\";\n> +\t\treg = <0xb011000 0x1000>;\n> +\t\t#mbox-cells = <1>;\n> +\n> +\t\tapcs_clk: apcs_clk {\n\nThis node describes that your implementation is split in two different\ndrivers.\n\nIn other words, I think you should add the two clock properties to the\napcs node, rather than adding a subnode. I also think you can make the\nmailbox driver implement the clock given the 8916 compatible.\n\n> +\t\t\tcompatible = \"qcom,msm8916-apcs-clk\";\n> +\t\t\tclocks = <&a53pll>;\n> +\t\t\t#clock-cells = <0>;\n> +\t\t};\n> +\t};\n\nRegards,\nBjorn\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"CYKqjcHz\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yMtsr5yLkz9t3J\n\tfor ;\n\tThu, 26 Oct 2017 15:13:36 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932274AbdJZENe (ORCPT );\n\tThu, 26 Oct 2017 00:13:34 -0400","from mail-pg0-f65.google.com ([74.125.83.65]:52024 \"EHLO\n\tmail-pg0-f65.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751460AbdJZEN1 (ORCPT\n\t); Thu, 26 Oct 2017 00:13:27 -0400","by mail-pg0-f65.google.com with SMTP id p9so1692189pgc.8\n\tfor ;\n\tWed, 25 Oct 2017 21:13:27 -0700 (PDT)","from tuxbook (ip68-111-217-79.sd.sd.cox.net. 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