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GET /api/patches/816819/?format=api
{ "id": 816819, "url": "http://patchwork.ozlabs.org/api/patches/816819/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/patch/1505992913-107256-2-git-send-email-linyunsheng@huawei.com/", "project": { "id": 7, "url": "http://patchwork.ozlabs.org/api/projects/7/?format=api", "name": "Linux network development", "link_name": "netdev", "list_id": "netdev.vger.kernel.org", "list_email": "netdev@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505992913-107256-2-git-send-email-linyunsheng@huawei.com>", "list_archive_url": null, "date": "2017-09-21T11:21:44", "name": "[net-next,01/10] net: hns3: Support for dynamically assigning tx buffer to TC", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "4b1cc5e987029df87ab3eb4d3dcffe9d50a1a31d", "submitter": { "id": 71804, "url": "http://patchwork.ozlabs.org/api/people/71804/?format=api", "name": "Yunsheng Lin", "email": "linyunsheng@huawei.com" }, "delegate": { "id": 34, "url": "http://patchwork.ozlabs.org/api/users/34/?format=api", "username": "davem", "first_name": "David", "last_name": "Miller", "email": "davem@davemloft.net" }, "mbox": "http://patchwork.ozlabs.org/project/netdev/patch/1505992913-107256-2-git-send-email-linyunsheng@huawei.com/mbox/", "series": [ { "id": 4360, "url": "http://patchwork.ozlabs.org/api/series/4360/?format=api", "web_url": "http://patchwork.ozlabs.org/project/netdev/list/?series=4360", "date": "2017-09-21T11:21:52", "name": "Add support for DCB feature in hns3 driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/4360/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/816819/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/816819/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<netdev-owner@vger.kernel.org>", "X-Original-To": "patchwork-incoming@ozlabs.org", "Delivered-To": "patchwork-incoming@ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyZ7P27xnz9t42\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 21 Sep 2017 21:26:25 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751737AbdIULWT (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tThu, 21 Sep 2017 07:22:19 -0400", "from szxga04-in.huawei.com ([45.249.212.190]:6953 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751617AbdIULWR (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Thu, 21 Sep 2017 07:22:17 -0400", "from 172.30.72.58 (EHLO DGGEMS408-HUB.china.huawei.com)\n\t([172.30.72.58])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DHR44628; Thu, 21 Sep 2017 19:22:14 +0800 (CST)", "from localhost.localdomain (10.67.212.75) by\n\tDGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP\n\tServer id 14.3.301.0; Thu, 21 Sep 2017 19:22:08 +0800" ], "From": "Yunsheng Lin <linyunsheng@huawei.com>", "To": "<davem@davemloft.net>", "CC": "<huangdaode@hisilicon.com>, <xuwei5@hisilicon.com>,\n\t<liguozhu@hisilicon.com>, <Yisen.Zhuang@huawei.com>,\n\t<gabriele.paoloni@huawei.com>, <john.garry@huawei.com>,\n\t<linuxarm@huawei.com>, <yisen.zhuang@huawei.com>,\n\t<salil.mehta@huawei.com>, <lipeng321@huawei.com>,\n\t<netdev@vger.kernel.org>, <linux-kernel@vger.kernel.org>", "Subject": "[PATCH net-next 01/10] net: hns3: Support for dynamically assigning\n\ttx buffer to TC", "Date": "Thu, 21 Sep 2017 19:21:44 +0800", "Message-ID": "<1505992913-107256-2-git-send-email-linyunsheng@huawei.com>", "X-Mailer": "git-send-email 1.9.1", "In-Reply-To": "<1505992913-107256-1-git-send-email-linyunsheng@huawei.com>", "References": "<1505992913-107256-1-git-send-email-linyunsheng@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.67.212.75]", "X-CFilter-Loop": "Reflected", "X-Mirapoint-Virus-RAPID-Raw": "score=unknown(0),\n\trefid=str=0001.0A090205.59C3A0E7.0260, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32", "X-Mirapoint-Loop-Id": "18e826654fd50a553155bd3775c53bef", "Sender": "netdev-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<netdev.vger.kernel.org>", "X-Mailing-List": "netdev@vger.kernel.org" }, "content": "This patch add support of dynamically assigning tx buffer to\nTC when the TC is enabled.\nIt will save buffer for rx direction to avoid packet loss.\n\nSigned-off-by: Yunsheng Lin <linyunsheng@huawei.com>\n---\n .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 1 +\n .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 69 ++++++++++++++++++----\n 2 files changed, 60 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h\nindex 758cf39..a81c6cb 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h\n@@ -311,6 +311,7 @@ struct hclge_tc_thrd {\n struct hclge_priv_buf {\n \tstruct hclge_waterline wl;\t/* Waterline for low and high*/\n \tu32 buf_size;\t/* TC private buffer size */\n+\tu32 tx_buf_size;\n \tu32 enable;\t/* Enable TC private buffer or not */\n };\n \ndiff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\nindex d27618b..dfe0fd2 100644\n--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\n+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c\n@@ -1324,23 +1324,28 @@ static int hclge_alloc_vport(struct hclge_dev *hdev)\n \treturn 0;\n }\n \n-static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, u16 buf_size)\n+static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev)\n {\n /* TX buffer size is unit by 128 byte */\n #define HCLGE_BUF_SIZE_UNIT_SHIFT\t7\n #define HCLGE_BUF_SIZE_UPDATE_EN_MSK\tBIT(15)\n \tstruct hclge_tx_buff_alloc *req;\n+\tstruct hclge_priv_buf *priv;\n \tstruct hclge_desc desc;\n+\tu32 buf_size;\n \tint ret;\n \tu8 i;\n \n \treq = (struct hclge_tx_buff_alloc *)desc.data;\n \n \thclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);\n-\tfor (i = 0; i < HCLGE_TC_NUM; i++)\n+\tfor (i = 0; i < HCLGE_TC_NUM; i++) {\n+\t\tpriv = &hdev->priv_buf[i];\n+\t\tbuf_size = priv->tx_buf_size;\n \t\treq->tx_pkt_buff[i] =\n \t\t\tcpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |\n \t\t\t\t HCLGE_BUF_SIZE_UPDATE_EN_MSK);\n+\t}\n \n \tret = hclge_cmd_send(&hdev->hw, &desc, 1);\n \tif (ret) {\n@@ -1352,9 +1357,9 @@ static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, u16 buf_size)\n \treturn 0;\n }\n \n-static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, u32 buf_size)\n+static int hclge_tx_buffer_alloc(struct hclge_dev *hdev)\n {\n-\tint ret = hclge_cmd_alloc_tx_buff(hdev, buf_size);\n+\tint ret = hclge_cmd_alloc_tx_buff(hdev);\n \n \tif (ret) {\n \t\tdev_err(&hdev->pdev->dev,\n@@ -1433,6 +1438,18 @@ static u32 hclge_get_rx_priv_buff_alloced(struct hclge_dev *hdev)\n \treturn rx_priv;\n }\n \n+static u32 hclge_get_tx_buff_alloced(struct hclge_dev *hdev)\n+{\n+\tstruct hclge_priv_buf *priv;\n+\tu32 tx_buf = 0, i;\n+\n+\tfor (i = 0; i < HCLGE_MAX_TC_NUM; i++) {\n+\t\tpriv = &hdev->priv_buf[i];\n+\t\ttx_buf += priv->tx_buf_size;\n+\t}\n+\treturn tx_buf;\n+}\n+\n static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, u32 rx_all)\n {\n \tu32 shared_buf_min, shared_buf_tc, shared_std;\n@@ -1477,18 +1494,44 @@ static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, u32 rx_all)\n \treturn true;\n }\n \n+static int hclge_tx_buffer_calc(struct hclge_dev *hdev)\n+{\n+\tstruct hclge_priv_buf *priv;\n+\tu32 i, total_size;\n+\n+\ttotal_size = hdev->pkt_buf_size;\n+\n+\t/* alloc tx buffer for all enabled tc */\n+\tfor (i = 0; i < HCLGE_MAX_TC_NUM; i++) {\n+\t\tpriv = &hdev->priv_buf[i];\n+\n+\t\tif (total_size < HCLGE_DEFAULT_TX_BUF)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tif (hdev->hw_tc_map & BIT(i))\n+\t\t\tpriv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;\n+\t\telse\n+\t\t\tpriv->tx_buf_size = 0;\n+\n+\t\ttotal_size -= priv->tx_buf_size;\n+\t}\n+\n+\treturn 0;\n+}\n+\n /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs\n * @hdev: pointer to struct hclge_dev\n- * @tx_size: the allocated tx buffer for all TCs\n * @return: 0: calculate sucessful, negative: fail\n */\n-int hclge_rx_buffer_calc(struct hclge_dev *hdev, u32 tx_size)\n+int hclge_rx_buffer_calc(struct hclge_dev *hdev)\n {\n-\tu32 rx_all = hdev->pkt_buf_size - tx_size;\n+\tu32 rx_all = hdev->pkt_buf_size;\n \tint no_pfc_priv_num, pfc_priv_num;\n \tstruct hclge_priv_buf *priv;\n \tint i;\n \n+\trx_all -= hclge_get_tx_buff_alloced(hdev);\n+\n \t/* When DCB is not supported, rx private\n \t * buffer is not allocated.\n \t */\n@@ -1771,7 +1814,6 @@ static int hclge_common_wl_config(struct hclge_dev *hdev)\n \n int hclge_buffer_alloc(struct hclge_dev *hdev)\n {\n-\tu32 tx_buf_size = HCLGE_DEFAULT_TX_BUF;\n \tint ret;\n \n \thdev->priv_buf = devm_kmalloc_array(&hdev->pdev->dev, HCLGE_MAX_TC_NUM,\n@@ -1780,14 +1822,21 @@ int hclge_buffer_alloc(struct hclge_dev *hdev)\n \tif (!hdev->priv_buf)\n \t\treturn -ENOMEM;\n \n-\tret = hclge_tx_buffer_alloc(hdev, tx_buf_size);\n+\tret = hclge_tx_buffer_calc(hdev);\n+\tif (ret) {\n+\t\tdev_err(&hdev->pdev->dev,\n+\t\t\t\"could not calc tx buffer size for all TCs %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tret = hclge_tx_buffer_alloc(hdev);\n \tif (ret) {\n \t\tdev_err(&hdev->pdev->dev,\n \t\t\t\"could not alloc tx buffers %d\\n\", ret);\n \t\treturn ret;\n \t}\n \n-\tret = hclge_rx_buffer_calc(hdev, tx_buf_size);\n+\tret = hclge_rx_buffer_calc(hdev);\n \tif (ret) {\n \t\tdev_err(&hdev->pdev->dev,\n \t\t\t\"could not calc rx priv buffer size for all TCs %d\\n\",\n", "prefixes": [ "net-next", "01/10" ] }