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GET /api/patches/815459/?format=api
{ "id": 815459, "url": "http://patchwork.ozlabs.org/api/patches/815459/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20170919105605.18533-3-vigneshr@ti.com/", "project": { "id": 3, "url": "http://patchwork.ozlabs.org/api/projects/3/?format=api", "name": "Linux MTD development", "link_name": "linux-mtd", "list_id": "linux-mtd.lists.infradead.org", "list_email": "linux-mtd@lists.infradead.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170919105605.18533-3-vigneshr@ti.com>", "list_archive_url": null, "date": "2017-09-19T10:56:02", "name": "[RESEND,v2,2/5] mtd: spi-nor: cadence-quadspi: add a delay in write sequence", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "871b89858f846eaf7371ee33ea9f72b801fd25a9", "submitter": { "id": 65039, "url": "http://patchwork.ozlabs.org/api/people/65039/?format=api", "name": "Raghavendra, Vignesh", "email": "vigneshr@ti.com" }, "delegate": { "id": 63396, "url": "http://patchwork.ozlabs.org/api/users/63396/?format=api", "username": "cpitchen", "first_name": "Cyrille", "last_name": "Pitchen", "email": "cyrille.pitchen@atmel.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-mtd/patch/20170919105605.18533-3-vigneshr@ti.com/mbox/", "series": [ { "id": 3841, "url": "http://patchwork.ozlabs.org/api/series/3841/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-mtd/list/?series=3841", "date": "2017-09-19T10:56:01", "name": "K2G: Add QSPI support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/3841/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815459/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815459/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org; 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Tue, 19 Sep 2017 11:11:10 +0000", "from lelnx194.ext.ti.com ([198.47.27.80])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duGDE-0002p3-UN; Tue, 19 Sep 2017 10:57:25 +0000", "from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8JAuHhs017698; \n\tTue, 19 Sep 2017 05:56:17 -0500", "from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8JAuHAT011847; \n\tTue, 19 Sep 2017 05:56:17 -0500", "from DLEE103.ent.ti.com (157.170.170.33) by DLEE112.ent.ti.com\n\t(157.170.170.23) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tTue, 19 Sep 2017 05:56:17 -0500", "from dlep32.itg.ti.com (157.170.170.100) by DLEE103.ent.ti.com\n\t(157.170.170.33) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Tue, 19 Sep 2017 05:56:17 -0500", "from a0132425.india.ti.com (ileax41-snat.itg.ti.com\n\t[10.172.224.153])\n\tby dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8JAu6Re022115;\n\tTue, 19 Sep 2017 05:56:14 -0500" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=Y5MvCSeZzgb7Q1hEAxDHOVm9heJ6eetUy0PbRe+Aheo=;\n\tb=qapaiAi4PXau/j\n\tCg8lbdMs4FOfvi8VIlsPA+M9yWcMm/zJcl4wfGZUmDEgpDQAR6zvkGmpIE4YxBn+ixVctT14z1F7b\n\tbUv0ZnDWhBufYlUdgADHu9NyIcuwXHjRFvRE4DjIeHvY4nnvBSk657G1/SGGOf2wrn3jf/fnasG3I\n\tVwmQKYv626NnT6yUmlzTjYt/zQ4JLl/J91hAOl58iohzvAZKAXPxBJ4vN/ZqClzQYbDr5kdqe+bR1\n\t8iBGJdPkz6U/IPjj59dwiREpC3KVZe2W+IPbU0xhXoXoMHcF80tneMWlcL7GahmMn96bI4CSC8VW5\n\tJ/tjNiXRFvS+uPQXJcqA==;", "v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1505818577;\n\tbh=2EuXtWQIl3bScAvK2WQoLGQuoRvvwa1bhw8VvgXP/9k=;\n\th=From:To:CC:Subject:Date:In-Reply-To:References;\n\tb=lopbFTakjIteM6qSvxrkK+y5viFUTxziEQqOKbCJFdTtYjM6ygBT/fzylxkA9ex+Q\n\toZH4WQXglZCQ93ol1Dl7cdGB/P+qMYb2Bi1oA8+QBjwdCs/CB8bbim21nI8F1TmbTp\n\tms2A5NEUilUHgm11m2huuNtpebGJWKeZLKGSp8ls=" ], "From": "Vignesh R <vigneshr@ti.com>", "To": "Marek Vasut <marek.vasut@gmail.com>, Cyrille Pitchen\n\t<cyrille.pitchen@wedev4u.fr>", "Subject": "[RESEND PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence", "Date": "Tue, 19 Sep 2017 16:26:02 +0530", "Message-ID": "<20170919105605.18533-3-vigneshr@ti.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170919105605.18533-1-vigneshr@ti.com>", "References": "<20170919105605.18533-1-vigneshr@ti.com>", "MIME-Version": "1.0", "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20170919_035709_149911_20113290 ", "X-CRM114-Status": "GOOD ( 11.85 )", "X-Spam-Score": "-2.0 (--)", "X-Spam-Report": "SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [198.47.27.80 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain", "X-BeenThere": "linux-mtd@lists.infradead.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "Linux MTD discussion mailing list <linux-mtd.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-mtd/>", "List-Post": "<mailto:linux-mtd@lists.infradead.org>", "List-Help": "<mailto:linux-mtd-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-mtd>,\n\t<mailto:linux-mtd-request@lists.infradead.org?subject=subscribe>", "Cc": "Boris Brezillon <boris.brezillon@free-electrons.com>,\n\tVignesh R <vigneshr@ti.com>, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,\n\tlinux-mtd@lists.infradead.org,\n\tBrian Norris <computersforpeace@gmail.com>, \n\tDavid Woodhouse <dwmw2@infradead.org>,\n\tlinux-arm-kernel <linux-arm-kernel@lists.infradead.org>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-mtd\" <linux-mtd-bounces@lists.infradead.org>", "Errors-To": "linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access\nController programming sequence, a delay equal to couple of QSPI master\nclock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and\nwriting data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY\nto handle this and set this flag for TI 66AK2G SoC.\n\n[1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf\n\nSigned-off-by: Vignesh R <vigneshr@ti.com>\n---\n drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-\n 1 file changed, 26 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\nindex 53c7d8e0327a..bb0cb02a6938 100644\n--- a/drivers/mtd/spi-nor/cadence-quadspi.c\n+++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n@@ -38,6 +38,9 @@\n #define CQSPI_NAME\t\t\t\"cadence-qspi\"\n #define CQSPI_MAX_CHIPSELECT\t\t16\n \n+/* Quirks */\n+#define CQSPI_NEEDS_WR_DELAY\t\tBIT(0)\n+\n struct cqspi_st;\n \n struct cqspi_flash_pdata {\n@@ -76,6 +79,7 @@ struct cqspi_st {\n \tu32\t\t\tfifo_depth;\n \tu32\t\t\tfifo_width;\n \tu32\t\t\ttrigger_address;\n+\tu32\t\t\twr_delay;\n \tstruct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];\n };\n \n@@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,\n \treinit_completion(&cqspi->transfer_complete);\n \twritel(CQSPI_REG_INDIRECTWR_START_MASK,\n \t reg_base + CQSPI_REG_INDIRECTWR);\n+\t/*\n+\t * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access\n+\t * Controller programming sequence, couple of cycles of\n+\t * QSPI_REF_CLK delay is required for the above bit to\n+\t * be internally synchronized by the QSPI module. Provide 5\n+\t * cycles of delay.\n+\t */\n+\tif (cqspi->wr_delay)\n+\t\tndelay(cqspi->wr_delay);\n \n \twhile (remaining > 0) {\n \t\twrite_bytes = remaining > page_size ? page_size : remaining;\n@@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)\n \tstruct cqspi_st *cqspi;\n \tstruct resource *res;\n \tstruct resource *res_ahb;\n+\tu32 data;\n \tint ret;\n \tint irq;\n \n@@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)\n \t}\n \n \tcqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);\n+\tdata = (u32)of_device_get_match_data(&pdev->dev);\n+\tif (data & CQSPI_NEEDS_WR_DELAY)\n+\t\tcqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,\n+\t\t\t\t\t\t cqspi->master_ref_clk_hz);\n \n \tret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,\n \t\t\t pdev->name, cqspi);\n@@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {\n #endif\n \n static const struct of_device_id cqspi_dt_ids[] = {\n-\t{.compatible = \"cdns,qspi-nor\",},\n+\t{\n+\t\t.compatible = \"cdns,qspi-nor\",\n+\t\t.data = (void *)0,\n+\t},\n+\t{\n+\t\t.compatible = \"ti,k2g-qspi\",\n+\t\t.data = (void *)CQSPI_NEEDS_WR_DELAY,\n+\t},\n \t{ /* end of table */ }\n };\n \n", "prefixes": [ "RESEND", "v2", "2/5" ] }