[{"id":1773343,"web_url":"http://patchwork.ozlabs.org/comment/1773343/","msgid":"<201709221614.9GmeyqNH%fengguang.wu@intel.com>","list_archive_url":null,"date":"2017-09-22T08:04:41","subject":"Re: [RESEND PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay\n\tin write sequence","submitter":{"id":67315,"url":"http://patchwork.ozlabs.org/api/people/67315/","name":"kernel test robot","email":"lkp@intel.com"},"content":"Hi Vignesh,\n\n[auto build test WARNING on l2-mtd-boris/spi-nor/next]\n[also build test WARNING on v4.14-rc1 next-20170921]\n[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]\n\nurl: https://github.com/0day-ci/linux/commits/Vignesh-R/K2G-Add-QSPI-support/20170922-152110\nbase: git://git.infradead.org/l2-mtd.git spi-nor/next\nconfig: sparc64-allmodconfig (attached as .config)\ncompiler: sparc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705\nreproduce:\n wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross\n chmod +x ~/bin/make.cross\n # save the attached .config to linux build tree\n make.cross ARCH=sparc64 \n\nAll warnings (new ones prefixed by >>):\n\n drivers/mtd/spi-nor/cadence-quadspi.c: In function 'cqspi_probe':\n>> drivers/mtd/spi-nor/cadence-quadspi.c:1230:10: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]\n data = (u32)of_device_get_match_data(&pdev->dev);\n ^\n\nvim +1230 drivers/mtd/spi-nor/cadence-quadspi.c\n\n 1164\t\n 1165\tstatic int cqspi_probe(struct platform_device *pdev)\n 1166\t{\n 1167\t\tstruct device_node *np = pdev->dev.of_node;\n 1168\t\tstruct device *dev = &pdev->dev;\n 1169\t\tstruct cqspi_st *cqspi;\n 1170\t\tstruct resource *res;\n 1171\t\tstruct resource *res_ahb;\n 1172\t\tu32 data;\n 1173\t\tint ret;\n 1174\t\tint irq;\n 1175\t\n 1176\t\tcqspi = devm_kzalloc(dev, sizeof(*cqspi), GFP_KERNEL);\n 1177\t\tif (!cqspi)\n 1178\t\t\treturn -ENOMEM;\n 1179\t\n 1180\t\tmutex_init(&cqspi->bus_mutex);\n 1181\t\tcqspi->pdev = pdev;\n 1182\t\tplatform_set_drvdata(pdev, cqspi);\n 1183\t\n 1184\t\t/* Obtain configuration from OF. */\n 1185\t\tret = cqspi_of_get_pdata(pdev);\n 1186\t\tif (ret) {\n 1187\t\t\tdev_err(dev, \"Cannot get mandatory OF data.\\n\");\n 1188\t\t\treturn -ENODEV;\n 1189\t\t}\n 1190\t\n 1191\t\t/* Obtain QSPI clock. */\n 1192\t\tcqspi->clk = devm_clk_get(dev, NULL);\n 1193\t\tif (IS_ERR(cqspi->clk)) {\n 1194\t\t\tdev_err(dev, \"Cannot claim QSPI clock.\\n\");\n 1195\t\t\treturn PTR_ERR(cqspi->clk);\n 1196\t\t}\n 1197\t\n 1198\t\t/* Obtain and remap controller address. */\n 1199\t\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n 1200\t\tcqspi->iobase = devm_ioremap_resource(dev, res);\n 1201\t\tif (IS_ERR(cqspi->iobase)) {\n 1202\t\t\tdev_err(dev, \"Cannot remap controller address.\\n\");\n 1203\t\t\treturn PTR_ERR(cqspi->iobase);\n 1204\t\t}\n 1205\t\n 1206\t\t/* Obtain and remap AHB address. */\n 1207\t\tres_ahb = platform_get_resource(pdev, IORESOURCE_MEM, 1);\n 1208\t\tcqspi->ahb_base = devm_ioremap_resource(dev, res_ahb);\n 1209\t\tif (IS_ERR(cqspi->ahb_base)) {\n 1210\t\t\tdev_err(dev, \"Cannot remap AHB address.\\n\");\n 1211\t\t\treturn PTR_ERR(cqspi->ahb_base);\n 1212\t\t}\n 1213\t\n 1214\t\tinit_completion(&cqspi->transfer_complete);\n 1215\t\n 1216\t\t/* Obtain IRQ line. */\n 1217\t\tirq = platform_get_irq(pdev, 0);\n 1218\t\tif (irq < 0) {\n 1219\t\t\tdev_err(dev, \"Cannot obtain IRQ.\\n\");\n 1220\t\t\treturn -ENXIO;\n 1221\t\t}\n 1222\t\n 1223\t\tret = clk_prepare_enable(cqspi->clk);\n 1224\t\tif (ret) {\n 1225\t\t\tdev_err(dev, \"Cannot enable QSPI clock.\\n\");\n 1226\t\t\treturn ret;\n 1227\t\t}\n 1228\t\n 1229\t\tcqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);\n> 1230\t\tdata = (u32)of_device_get_match_data(&pdev->dev);\n 1231\t\tif (data & CQSPI_NEEDS_WR_DELAY)\n 1232\t\t\tcqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,\n 1233\t\t\t\t\t\t\t cqspi->master_ref_clk_hz);\n 1234\t\n 1235\t\tret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,\n 1236\t\t\t\t pdev->name, cqspi);\n 1237\t\tif (ret) {\n 1238\t\t\tdev_err(dev, \"Cannot request IRQ.\\n\");\n 1239\t\t\tgoto probe_irq_failed;\n 1240\t\t}\n 1241\t\n 1242\t\tcqspi_wait_idle(cqspi);\n 1243\t\tcqspi_controller_init(cqspi);\n 1244\t\tcqspi->current_cs = -1;\n 1245\t\tcqspi->sclk = 0;\n 1246\t\n 1247\t\tret = cqspi_setup_flash(cqspi, np);\n 1248\t\tif (ret) {\n 1249\t\t\tdev_err(dev, \"Cadence QSPI NOR probe failed %d\\n\", ret);\n 1250\t\t\tgoto probe_setup_failed;\n 1251\t\t}\n 1252\t\n 1253\t\treturn ret;\n 1254\tprobe_irq_failed:\n 1255\t\tcqspi_controller_enable(cqspi, 0);\n 1256\tprobe_setup_failed:\n 1257\t\tclk_disable_unprepare(cqspi->clk);\n 1258\t\treturn ret;\n 1259\t}\n 1260\t\n\n---\n0-DAY kernel test infrastructure Open Source Technology Center\nhttps://lists.01.org/pipermail/kbuild-all Intel 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","Subject":"Re: [RESEND PATCH v2 2/5] mtd: spi-nor: cadence-quadspi: add a delay\n\tin write sequence","Message-ID":"<201709221614.9GmeyqNH%fengguang.wu@intel.com>","MIME-Version":"1.0","Content-Type":"multipart/mixed; boundary=\"AhhlLboLdkugWU4S\"","Content-Disposition":"inline","In-Reply-To":"<20170919105605.18533-3-vigneshr@ti.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","X-SA-Exim-Connect-IP":"","X-SA-Exim-Mail-From":"fengguang.wu@intel.com","X-SA-Exim-Scanned":"No (on bee); SAEximRunCond expanded to false","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170922_010532_306196_6B5BBA01 ","X-CRM114-Status":"GOOD ( 16.94 )","X-Spam-Score":"-5.4 (-----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-5.4 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed 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