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GET /api/patches/815359/?format=api
{ "id": 815359, "url": "http://patchwork.ozlabs.org/api/patches/815359/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-2-git-send-email-chin.liang.see@intel.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505812951-25088-2-git-send-email-chin.liang.see@intel.com>", "list_archive_url": null, "date": "2017-09-19T09:22:18", "name": "[U-Boot,01/14] arm: socfpga: stratix10: Add base address map for Statix10 SoC", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "b91e2b552e65421396a19dcd248492c8b6a49d7f", "submitter": { "id": 70182, "url": "http://patchwork.ozlabs.org/api/people/70182/?format=api", "name": "See, Chin Liang", "email": "chin.liang.see@intel.com" }, "delegate": { "id": 1699, "url": "http://patchwork.ozlabs.org/api/users/1699/?format=api", "username": "marex", "first_name": "Marek", "last_name": "Vasut", "email": "marek.vasut@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1505812951-25088-2-git-send-email-chin.liang.see@intel.com/mbox/", "series": [ { "id": 3810, "url": "http://patchwork.ozlabs.org/api/series/3810/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=3810", "date": "2017-09-19T09:22:17", "name": "Enable Stratix10 SoC support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/3810/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/815359/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/815359/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxHWQ182gz9ryr\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 19 Sep 2017 19:24:18 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid D360BC21DD1; Tue, 19 Sep 2017 09:23:42 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 49462C21ECC;\n\tTue, 19 Sep 2017 09:23:22 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid AB983C21DD1; Tue, 19 Sep 2017 09:23:19 +0000 (UTC)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n\tby lists.denx.de (Postfix) with ESMTPS id 0652BC21D55\n\tfor <u-boot@lists.denx.de>; Tue, 19 Sep 2017 09:23:17 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t19 Sep 2017 02:23:13 -0700", "from pg-interactive1.altera.com ([137.57.137.156])\n\tby fmsmga002.fm.intel.com with ESMTP; 19 Sep 2017 02:22:39 -0700" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-5.0 required=5.0 tests=RCVD_IN_DNSWL_HI\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos; i=\"5.42,417,1500966000\"; d=\"scan'208\";\n\ta=\"1220781660\"", "From": "chin.liang.see@intel.com", "To": "u-boot@lists.denx.de,\n\tMarek Vasut <marex@denx.de>", "Date": "Tue, 19 Sep 2017 17:22:18 +0800", "Message-Id": "<1505812951-25088-2-git-send-email-chin.liang.see@intel.com>", "X-Mailer": "git-send-email 2.2.2", "In-Reply-To": "<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>", "References": "<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>", "Cc": "Tien Fong Chee <tien.fong.chee@intel.com>,\n\tChin Liang See <chin.liang.see@intel.com>", "Subject": "[U-Boot] [PATCH 01/14] arm: socfpga: stratix10: Add base address\n\tmap for Statix10 SoC", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Chin Liang See <chin.liang.see@intel.com>\n\nAdd the base address map for Statix10 SoC\n\nSigned-off-by: Chin Liang See <chin.liang.see@intel.com>\n---\n arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 58 ++++++++++++++++++++++\n 1 file changed, 58 insertions(+)\n create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h", "diff": "diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h\nnew file mode 100644\nindex 0000000..feb1881\n--- /dev/null\n+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h\n@@ -0,0 +1,58 @@\n+/*\n+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0\n+ */\n+\n+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_\n+#define _SOCFPGA_S10_BASE_HARDWARE_H_\n+\n+#define SOCFPGA_SDR_SCHEDULER_ADDRESS\t\t0xf8000400\n+#define SOCFPGA_HMC_MMR_IO48_ADDRESS\t\t0xf8010000\n+#define SOCFPGA_SDR_ADDRESS\t\t\t0xf8011000\n+#define SOCFPGA_SMMU_ADDRESS\t\t\t0xfa000000\n+#define SOCFPGA_EMAC0_ADDRESS\t\t\t0xff800000\n+#define SOCFPGA_EMAC1_ADDRESS\t\t\t0xff802000\n+#define SOCFPGA_EMAC2_ADDRESS\t\t\t0xff804000\n+#define SOCFPGA_SDMMC_ADDRESS\t\t\t0xff808000\n+#define SOCFPGA_QSPIREGS_ADDRESS\t\t0xff8d2000\n+#define SOCFPGA_QSPIDATA_ADDRESS\t\t0xff900000\n+#define SOCFPGA_MAILBOX_ADDRESS\t\t\t0xffA30000\n+#define SOCFPGA_USB0_ADDRESS\t\t\t0xffb00000\n+#define SOCFPGA_USB1_ADDRESS\t\t\t0xffb40000\n+#define SOCFPGA_NANDREGS_ADDRESS\t\t0xffb80000\n+#define SOCFPGA_NANDDATA_ADDRESS\t\t0xffb90000\n+#define SOCFPGA_UART0_ADDRESS\t\t\t0xffc02000\n+#define SOCFPGA_UART1_ADDRESS\t\t\t0xffc02100\n+#define SOCFPGA_I2C0_ADDRESS\t\t\t0xffc02800\n+#define SOCFPGA_I2C1_ADDRESS\t\t\t0xffc02900\n+#define SOCFPGA_I2C2_ADDRESS\t\t\t0xffc02a00\n+#define SOCFPGA_I2C3_ADDRESS\t\t\t0xffc02b00\n+#define SOCFPGA_I2C4_ADDRESS\t\t\t0xffc02c00\n+#define SOCFPGA_SPTIMER0_ADDRESS\t\t0xffc03000\n+#define SOCFPGA_SPTIMER1_ADDRESS\t\t0xffc03100\n+#define SOCFPGA_GPIO0_ADDRESS\t\t\t0xffc03200\n+#define SOCFPGA_GPIO1_ADDRESS\t\t\t0xffc03300\n+#define SOCFPGA_SYSTIMER0_ADDRESS\t\t0xffd00000\n+#define SOCFPGA_SYSTIMER1_ADDRESS\t\t0xffd00100\n+#define SOCFPGA_L4WD0_ADDRESS\t\t\t0xffd00200\n+#define SOCFPGA_L4WD1_ADDRESS\t\t\t0xffd00300\n+#define SOCFPGA_L4WD2_ADDRESS\t\t\t0xffd00400\n+#define SOCFPGA_L4WD3_ADDRESS\t\t\t0xffd00500\n+#define SOCFPGA_GTIMER_SEC_ADDRESS\t\t0xffd01000\n+#define SOCFPGA_GTIMER_NSEC_ADDRESS\t\t0xffd02000\n+#define SOCFPGA_CLKMGR_ADDRESS\t\t\t0xffd10000\n+#define SOCFPGA_RSTMGR_ADDRESS\t\t\t0xffd11000\n+#define SOCFPGA_SYSMGR_ADDRESS\t\t\t0xffd12000\n+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS\t0xffd13000\n+#define SOCFPGA_DMANONSECURE_ADDRESS\t\t0xffda0000\n+#define SOCFPGA_DMASECURE_ADDRESS\t\t0xffda1000\n+#define SOCFPGA_SPIS0_ADDRESS\t\t\t0xffda2000\n+#define SOCFPGA_SPIS1_ADDRESS\t\t\t0xffda3000\n+#define SOCFPGA_SPIM0_ADDRESS\t\t\t0xffda4000\n+#define SOCFPGA_SPIM1_ADDRESS\t\t\t0xffda5000\n+#define SOCFPGA_OCRAM_ADDRESS\t\t\t0xffe00000\n+#define GICD_BASE\t\t\t\t0xfffc1000\n+#define GICC_BASE\t\t\t\t0xfffc2000\n+\n+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */\n", "prefixes": [ "U-Boot", "01/14" ] }