[{"id":1770805,"web_url":"http://patchwork.ozlabs.org/comment/1770805/","msgid":"","list_archive_url":null,"date":"2017-09-19T09:51:34","subject":"Re: [U-Boot] [PATCH 01/14] arm: socfpga: stratix10: Add base\n\taddress map for Statix10 SoC","submitter":{"id":12009,"url":"http://patchwork.ozlabs.org/api/people/12009/","name":"Marek Vasut","email":"marex@denx.de"},"content":"On 09/19/2017 11:22 AM, chin.liang.see@intel.com wrote:\n> From: Chin Liang See \n> \n> Add the base address map for Statix10 SoC\n> \n> Signed-off-by: Chin Liang See \n\nAdd only the stuff which is not obtainable from DT please.\n\n> ---\n> arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 58 ++++++++++++++++++++++\n> 1 file changed, 58 insertions(+)\n> create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h\n> \n> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h\n> new file mode 100644\n> index 0000000..feb1881\n> --- /dev/null\n> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h\n> @@ -0,0 +1,58 @@\n> +/*\n> + * Copyright (C) 2016-2017 Intel Corporation \n> + *\n> + * SPDX-License-Identifier:\tGPL-2.0\n> + */\n> +\n> +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_\n> +#define _SOCFPGA_S10_BASE_HARDWARE_H_\n> +\n> +#define SOCFPGA_SDR_SCHEDULER_ADDRESS\t\t0xf8000400\n> +#define SOCFPGA_HMC_MMR_IO48_ADDRESS\t\t0xf8010000\n> +#define SOCFPGA_SDR_ADDRESS\t\t\t0xf8011000\n> +#define SOCFPGA_SMMU_ADDRESS\t\t\t0xfa000000\n> +#define SOCFPGA_EMAC0_ADDRESS\t\t\t0xff800000\n> +#define SOCFPGA_EMAC1_ADDRESS\t\t\t0xff802000\n> +#define SOCFPGA_EMAC2_ADDRESS\t\t\t0xff804000\n> +#define SOCFPGA_SDMMC_ADDRESS\t\t\t0xff808000\n> +#define SOCFPGA_QSPIREGS_ADDRESS\t\t0xff8d2000\n> +#define SOCFPGA_QSPIDATA_ADDRESS\t\t0xff900000\n> +#define SOCFPGA_MAILBOX_ADDRESS\t\t\t0xffA30000\n> +#define SOCFPGA_USB0_ADDRESS\t\t\t0xffb00000\n> +#define SOCFPGA_USB1_ADDRESS\t\t\t0xffb40000\n> +#define SOCFPGA_NANDREGS_ADDRESS\t\t0xffb80000\n> +#define SOCFPGA_NANDDATA_ADDRESS\t\t0xffb90000\n> +#define SOCFPGA_UART0_ADDRESS\t\t\t0xffc02000\n> +#define SOCFPGA_UART1_ADDRESS\t\t\t0xffc02100\n> +#define SOCFPGA_I2C0_ADDRESS\t\t\t0xffc02800\n> +#define SOCFPGA_I2C1_ADDRESS\t\t\t0xffc02900\n> +#define SOCFPGA_I2C2_ADDRESS\t\t\t0xffc02a00\n> +#define SOCFPGA_I2C3_ADDRESS\t\t\t0xffc02b00\n> +#define SOCFPGA_I2C4_ADDRESS\t\t\t0xffc02c00\n> +#define SOCFPGA_SPTIMER0_ADDRESS\t\t0xffc03000\n> +#define SOCFPGA_SPTIMER1_ADDRESS\t\t0xffc03100\n> +#define SOCFPGA_GPIO0_ADDRESS\t\t\t0xffc03200\n> +#define SOCFPGA_GPIO1_ADDRESS\t\t\t0xffc03300\n> +#define SOCFPGA_SYSTIMER0_ADDRESS\t\t0xffd00000\n> +#define SOCFPGA_SYSTIMER1_ADDRESS\t\t0xffd00100\n> +#define SOCFPGA_L4WD0_ADDRESS\t\t\t0xffd00200\n> +#define SOCFPGA_L4WD1_ADDRESS\t\t\t0xffd00300\n> +#define SOCFPGA_L4WD2_ADDRESS\t\t\t0xffd00400\n> +#define SOCFPGA_L4WD3_ADDRESS\t\t\t0xffd00500\n> +#define SOCFPGA_GTIMER_SEC_ADDRESS\t\t0xffd01000\n> +#define SOCFPGA_GTIMER_NSEC_ADDRESS\t\t0xffd02000\n> +#define SOCFPGA_CLKMGR_ADDRESS\t\t\t0xffd10000\n> +#define SOCFPGA_RSTMGR_ADDRESS\t\t\t0xffd11000\n> +#define SOCFPGA_SYSMGR_ADDRESS\t\t\t0xffd12000\n> +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS\t0xffd13000\n> +#define SOCFPGA_DMANONSECURE_ADDRESS\t\t0xffda0000\n> +#define SOCFPGA_DMASECURE_ADDRESS\t\t0xffda1000\n> +#define SOCFPGA_SPIS0_ADDRESS\t\t\t0xffda2000\n> +#define SOCFPGA_SPIS1_ADDRESS\t\t\t0xffda3000\n> +#define SOCFPGA_SPIM0_ADDRESS\t\t\t0xffda4000\n> +#define SOCFPGA_SPIM1_ADDRESS\t\t\t0xffda5000\n> +#define SOCFPGA_OCRAM_ADDRESS\t\t\t0xffe00000\n> +#define GICD_BASE\t\t\t\t0xfffc1000\n> +#define GICC_BASE\t\t\t\t0xfffc2000\n> +\n> +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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mnet-online.de","X-Auth-Info":"0FxDIIReUy1Wm07/eeIvZocYLVgNMhbPWsFdfVfhAqg=","To":"chin.liang.see@intel.com, u-boot@lists.denx.de","References":"<1505812951-25088-1-git-send-email-chin.liang.see@intel.com>\n\t<1505812951-25088-2-git-send-email-chin.liang.see@intel.com>","From":"Marek Vasut ","Message-ID":"","Date":"Tue, 19 Sep 2017 11:51:34 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1505812951-25088-2-git-send-email-chin.liang.see@intel.com>","Content-Language":"en-US","Cc":"Tien Fong Chee ","Subject":"Re: [U-Boot] [PATCH 01/14] arm: socfpga: stratix10: Add base\n\taddress map for Statix10 SoC","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1770987,"web_url":"http://patchwork.ozlabs.org/comment/1770987/","msgid":"<1505913252.2695.1.camel@intel.com>","list_archive_url":null,"date":"2017-09-19T13:13:18","subject":"Re: [U-Boot] [PATCH 01/14] arm: socfpga: stratix10: Add base\n\taddress map for Statix10 SoC","submitter":{"id":70182,"url":"http://patchwork.ozlabs.org/api/people/70182/","name":"See, Chin Liang","email":"chin.liang.see@intel.com"},"content":"On Tue, 2017-09-19 at 11:51 +0200, Marek Vasut wrote:\r\n> On 09/19/2017 11:22 AM, chin.liang.see@intel.com wrote:\r\n> > \r\n> > From: Chin Liang See \r\n> > \r\n> > Add the base address map for Statix10 SoC\r\n> > \r\n> > Signed-off-by: Chin Liang See \r\n> Add only the stuff which is not obtainable from DT please.\r\n> \r\n\r\nSure, let me remove the SDMMC, EMAC and QSPI since they are extracted\r\nfrom DT today\r\n\r\nThanks\r\nChin Liang\r\n\r\n> > \r\n> > ---\r\n> >  arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 58\r\n> > ++++++++++++++++++++++\r\n> >  1 file changed, 58 insertions(+)\r\n> >  create mode 100644 arch/arm/mach-\r\n> > socfpga/include/mach/base_addr_s10.h\r\n> > \r\n> > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h\r\n> > b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h\r\n> > new file mode 100644\r\n> > index 0000000..feb1881\r\n> > --- /dev/null\r\n> > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h\r\n> > @@ -0,0 +1,58 @@\r\n> > +/*\r\n> > + * Copyright (C) 2016-2017 Intel Corporation \r\n> > + *\r\n> > + * SPDX-License-Identifier:\tGPL-2.0\r\n> > + */\r\n> > +\r\n> > +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_\r\n> > +#define _SOCFPGA_S10_BASE_HARDWARE_H_\r\n> > +\r\n> > +#define SOCFPGA_SDR_SCHEDULER_ADDRESS\t\t0xf8000400\r\n> > +#define SOCFPGA_HMC_MMR_IO48_ADDRESS\t\t0xf8010000\r\n> > +#define SOCFPGA_SDR_ADDRESS\t\t\t0xf8011000\r\n> > +#define SOCFPGA_SMMU_ADDRESS\t\t\t0xfa000000\r\n> > +#define SOCFPGA_EMAC0_ADDRESS\t\t\t0xff800000\r\n> > +#define SOCFPGA_EMAC1_ADDRESS\t\t\t0xff802000\r\n> > +#define SOCFPGA_EMAC2_ADDRESS\t\t\t0xff804000\r\n> > +#define SOCFPGA_SDMMC_ADDRESS\t\t\t0xff808000\r\n> > +#define SOCFPGA_QSPIREGS_ADDRESS\t\t0xff8d2000\r\n> > +#define SOCFPGA_QSPIDATA_ADDRESS\t\t0xff900000\r\n> > +#define SOCFPGA_MAILBOX_ADDRESS\t\t\t0xffA30000\r\n> > +#define SOCFPGA_USB0_ADDRESS\t\t\t0xffb00000\r\n> > +#define SOCFPGA_USB1_ADDRESS\t\t\t0xffb40000\r\n> > +#define SOCFPGA_NANDREGS_ADDRESS\t\t0xffb80000\r\n> > +#define SOCFPGA_NANDDATA_ADDRESS\t\t0xffb90000\r\n> > +#define SOCFPGA_UART0_ADDRESS\t\t\t0xffc02000\r\n> > +#define SOCFPGA_UART1_ADDRESS\t\t\t0xffc02100\r\n> > +#define SOCFPGA_I2C0_ADDRESS\t\t\t0xffc02800\r\n> > +#define SOCFPGA_I2C1_ADDRESS\t\t\t0xffc02900\r\n> > +#define SOCFPGA_I2C2_ADDRESS\t\t\t0xffc02a00\r\n> > +#define SOCFPGA_I2C3_ADDRESS\t\t\t0xffc02b00\r\n> > +#define SOCFPGA_I2C4_ADDRESS\t\t\t0xffc02c00\r\n> > +#define SOCFPGA_SPTIMER0_ADDRESS\t\t0xffc03000\r\n> > +#define SOCFPGA_SPTIMER1_ADDRESS\t\t0xffc03100\r\n> > +#define SOCFPGA_GPIO0_ADDRESS\t\t\t0xffc03200\r\n> > +#define SOCFPGA_GPIO1_ADDRESS\t\t\t0xffc03300\r\n> > +#define SOCFPGA_SYSTIMER0_ADDRESS\t\t0xffd00000\r\n> > +#define SOCFPGA_SYSTIMER1_ADDRESS\t\t0xffd00100\r\n> > +#define SOCFPGA_L4WD0_ADDRESS\t\t\t0xffd00200\r\n> > +#define SOCFPGA_L4WD1_ADDRESS\t\t\t0xffd00300\r\n> > +#define SOCFPGA_L4WD2_ADDRESS\t\t\t0xffd00400\r\n> > +#define SOCFPGA_L4WD3_ADDRESS\t\t\t0xffd00500\r\n> > +#define SOCFPGA_GTIMER_SEC_ADDRESS\t\t0xffd01000\r\n> > +#define SOCFPGA_GTIMER_NSEC_ADDRESS\t\t0xffd02000\r\n> > +#define SOCFPGA_CLKMGR_ADDRESS\t\t\t0xffd10000\r\n> > +#define SOCFPGA_RSTMGR_ADDRESS\t\t\t0xffd11000\r\n> > +#define SOCFPGA_SYSMGR_ADDRESS\t\t\t0xffd12000\r\n> > +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS\t0xffd13000\r\n> > +#define SOCFPGA_DMANONSECURE_ADDRESS\t\t0xffda0000\r\n> > +#define SOCFPGA_DMASECURE_ADDRESS\t\t0xffda1000\r\n> > +#define SOCFPGA_SPIS0_ADDRESS\t\t\t0xffda2000\r\n> > +#define SOCFPGA_SPIS1_ADDRESS\t\t\t0xffda3000\r\n> > +#define SOCFPGA_SPIM0_ADDRESS\t\t\t0xffda4000\r\n> > +#define SOCFPGA_SPIM1_ADDRESS\t\t\t0xffda5000\r\n> > +#define SOCFPGA_OCRAM_ADDRESS\t\t\t0xffe00000\r\n> > +#define GICD_BASE\t\t\t\t0xfffc1000\r\n> > +#define GICC_BASE\t\t\t\t0xfffc2000\r\n> > +\r\n> > +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */\r\n> > \r\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxNby0BdMz9s4s\n\tfor ;\n\tTue, 19 Sep 2017 23:13:33 +1000 (AEST)","by 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Fong\" ","Subject":"Re: [U-Boot] [PATCH 01/14] arm: socfpga: stratix10: Add base\n\taddress map for Statix10 SoC","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]