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GET /api/patches/814360/?format=api
{ "id": 814360, "url": "http://patchwork.ozlabs.org/api/patches/814360/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170915190748.82389-1-jrtc27@jrtc27.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170915190748.82389-1-jrtc27@jrtc27.com>", "list_archive_url": null, "date": "2017-09-15T19:07:48", "name": "[v2] linux-user/syscall.c: Handle SH4's exceptional alignment for p{read, write}64", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ace964710d0311b93169b0b481984d71c581bf7f", "submitter": { "id": 64682, "url": "http://patchwork.ozlabs.org/api/people/64682/?format=api", "name": "Jessica Clarke", "email": "jrtc27@jrtc27.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170915190748.82389-1-jrtc27@jrtc27.com/mbox/", "series": [ { "id": 3354, "url": "http://patchwork.ozlabs.org/api/series/3354/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3354", "date": "2017-09-15T19:07:48", "name": "[v2] linux-user/syscall.c: Handle SH4's exceptional alignment for p{read, write}64", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/3354/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/814360/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/814360/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=jrtc27.com header.i=@jrtc27.com\n\theader.b=\"dhR+Dtqj\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xv4h42RyJz9s7g\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 16 Sep 2017 05:09:08 +1000 (AEST)", "from localhost ([::1]:54694 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dsvz8-00087I-Ep\n\tfor incoming@patchwork.ozlabs.org; Fri, 15 Sep 2017 15:09:06 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:53847)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <jrtc27@jrtc27.com>) id 1dsvyp-00086t-AZ\n\tfor qemu-devel@nongnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=jrtc27.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:references; bh=LGH4vp6VRiDp9W5F9efZgelvGwdWcGqoY+c85IFevhM=;\n\tb=dhR+Dtqj/1OMDjWMNXTW1aygDBEqTzDae44dv/2VR5v/r8ViRh++/jCpq7xgBtygyy\n\tFHy19Vt5AnUmBjQZl2TtcPW+oCo8t/MIzCsriLyEjpjkWNPZOr5gnGqgIOR53Wku+dRx\n\tm+Zavu3sFpLlEcUgXBld3sjyeuJLDgEknd5vU=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:references;\n\tbh=LGH4vp6VRiDp9W5F9efZgelvGwdWcGqoY+c85IFevhM=;\n\tb=BauOtEF1CZcaEgG9Vz+YBB15CwBLatVAnjwhWDrv76bN+kfnXtD6EYCnCEgdaOMOZw\n\tXZQvzixGEipGvVkg9LH1eEZebDvoq6dtfo8382beMdbSxomQNtaI2Ok0f7KiMFh3Yxiy\n\tC+I73feTZy3e1vxDujXHDSLMwCxrO7PwJ/E2Irot8cTvljKYLLHrow0QOGTXh4gEoSl1\n\tm+TaQb0lfuaoxgg43FproNS9J/v+orDKsPKHHyBT/z16ZVXyJWVRsvOc69Ur5FT2KZ68\n\tzWZJEvyS0g4PITGTNd2v6W38Gw30GB8icAv5C3mZlDHe/rK+tpF8f406aHJRp2t3H/Zc\n\thQfQ==", "X-Gm-Message-State": "AHPjjUgBNPxM+KklGZfSzbPoWruY/sxnhBfGnStR1xWP/n7QzhOFcHyn\n\tX+0Xc9Rg6CKUWzwQQB8LPZjStQ==", "X-Google-Smtp-Source": "AOwi7QCecub7FIBYAR4C4o9vELaGeHq0JI8m1K7ymDHq+RVkSFbBm634FE5iRsW9/KB0g1/h8xTt6w==", "X-Received": "by 10.28.57.215 with SMTP id g206mr3758051wma.117.1505502522497; \n\tFri, 15 Sep 2017 12:08:42 -0700 (PDT)", "From": "James Clarke <jrtc27@jrtc27.com>", "To": "QEMU Developers <qemu-devel@nongnu.org>", "Date": "Fri, 15 Sep 2017 20:07:48 +0100", "Message-Id": "<20170915190748.82389-1-jrtc27@jrtc27.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<cc5d79bb-a56a-08a6-c054-b194e6a5a833@linaro.org>", "References": [ "<cc5d79bb-a56a-08a6-c054-b194e6a5a833@linaro.org>", "<20170915065821.16600-1-jrtc27@jrtc27.com>\n\t<2f7283ca-6ecd-165f-c572-a0f2a781aba7@amsat.org>" ], "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2a00:1450:400c:c09::22f", "Subject": "[Qemu-devel] [PATCH v2] linux-user/syscall.c: Handle SH4's\n\texceptional alignment for p{read, write}64", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "Peter Maydell <peter.maydell@linaro.org>, Richard Henderson\n\t<richard.henderson@linaro.org>, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?=\n\t<f4bug@amsat.org>, \tLaurent Vivier <laurent@vivier.eu>,\n\tJohn Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>, \n\tJames Clarke <jrtc27@jrtc27.com>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Fixes: https://bugs.launchpad.net/qemu/+bug/1716767\nSigned-off-by: James Clarke <jrtc27@jrtc27.com>\n---\n\nChanges since v1:\n * Removed all changes in v1 :)\n * Added syscall num argument to regpairs_aligned\n * Added SH4-specific implementation of regpairs_aligned to return 1 for\n p{read,write}64\n\n linux-user/syscall.c | 34 +++++++++++++++++++++++-----------\n 1 file changed, 23 insertions(+), 11 deletions(-)", "diff": "diff --git a/linux-user/syscall.c b/linux-user/syscall.c\nindex 9b6364a266..492c654970 100644\n--- a/linux-user/syscall.c\n+++ b/linux-user/syscall.c\n@@ -667,18 +667,30 @@ static inline int next_free_host_timer(void)\n \n /* ARM EABI and MIPS expect 64bit types aligned even on pairs or registers */\n #ifdef TARGET_ARM\n-static inline int regpairs_aligned(void *cpu_env) {\n+static inline int regpairs_aligned(void *cpu_env, int num) {\n return ((((CPUARMState *)cpu_env)->eabi) == 1) ;\n }\n #elif defined(TARGET_MIPS) && (TARGET_ABI_BITS == 32)\n-static inline int regpairs_aligned(void *cpu_env) { return 1; }\n+static inline int regpairs_aligned(void *cpu_env, int num) { return 1; }\n #elif defined(TARGET_PPC) && !defined(TARGET_PPC64)\n /* SysV AVI for PPC32 expects 64bit parameters to be passed on odd/even pairs\n * of registers which translates to the same as ARM/MIPS, because we start with\n * r3 as arg1 */\n-static inline int regpairs_aligned(void *cpu_env) { return 1; }\n+static inline int regpairs_aligned(void *cpu_env, int num) { return 1; }\n+#elif defined(TARGET_SH4)\n+/* SH4 doesn't align register pairs, except for p{read,write}64 */\n+static inline int regpairs_aligned(void *cpu_env, int num) {\n+ switch (num) {\n+ case TARGET_NR_pread64:\n+ case TARGET_NR_pwrite64:\n+ return 1;\n+\n+ default:\n+ return 0;\n+ }\n+}\n #else\n-static inline int regpairs_aligned(void *cpu_env) { return 0; }\n+static inline int regpairs_aligned(void *cpu_env, int num) { return 0; }\n #endif\n \n #define ERRNO_TABLE_SIZE 1200\n@@ -6857,7 +6869,7 @@ static inline abi_long target_truncate64(void *cpu_env, const char *arg1,\n abi_long arg3,\n abi_long arg4)\n {\n- if (regpairs_aligned(cpu_env)) {\n+ if (regpairs_aligned(cpu_env, TARGET_NR_truncate64)) {\n arg2 = arg3;\n arg3 = arg4;\n }\n@@ -6871,7 +6883,7 @@ static inline abi_long target_ftruncate64(void *cpu_env, abi_long arg1,\n abi_long arg3,\n abi_long arg4)\n {\n- if (regpairs_aligned(cpu_env)) {\n+ if (regpairs_aligned(cpu_env, TARGET_NR_ftruncate64)) {\n arg2 = arg3;\n arg3 = arg4;\n }\n@@ -10495,7 +10507,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,\n #endif\n #ifdef TARGET_NR_pread64\n case TARGET_NR_pread64:\n- if (regpairs_aligned(cpu_env)) {\n+ if (regpairs_aligned(cpu_env, num)) {\n arg4 = arg5;\n arg5 = arg6;\n }\n@@ -10505,7 +10517,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,\n unlock_user(p, arg2, ret);\n break;\n case TARGET_NR_pwrite64:\n- if (regpairs_aligned(cpu_env)) {\n+ if (regpairs_aligned(cpu_env, num)) {\n arg4 = arg5;\n arg5 = arg6;\n }\n@@ -11275,7 +11287,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,\n arg6 = ret;\n #else\n /* 6 args: fd, offset (high, low), len (high, low), advice */\n- if (regpairs_aligned(cpu_env)) {\n+ if (regpairs_aligned(cpu_env, num)) {\n /* offset is in (3,4), len in (5,6) and advice in 7 */\n arg2 = arg3;\n arg3 = arg4;\n@@ -11294,7 +11306,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,\n #ifdef TARGET_NR_fadvise64\n case TARGET_NR_fadvise64:\n /* 5 args: fd, offset (high, low), len, advice */\n- if (regpairs_aligned(cpu_env)) {\n+ if (regpairs_aligned(cpu_env, num)) {\n /* offset is in (3,4), len in 5 and advice in 6 */\n arg2 = arg3;\n arg3 = arg4;\n@@ -11407,7 +11419,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,\n #ifdef TARGET_NR_readahead\n case TARGET_NR_readahead:\n #if TARGET_ABI_BITS == 32\n- if (regpairs_aligned(cpu_env)) {\n+ if (regpairs_aligned(cpu_env, num)) {\n arg2 = arg3;\n arg3 = arg4;\n arg4 = arg5;\n", "prefixes": [ "v2" ] }