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GET /api/patches/814329/?format=api
{ "id": 814329, "url": "http://patchwork.ozlabs.org/api/patches/814329/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505494753-10837-3-git-send-email-sundeep.lkml@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505494753-10837-3-git-send-email-sundeep.lkml@gmail.com>", "list_archive_url": null, "date": "2017-09-15T16:59:10", "name": "[Qemu,devel,v9,2/5] msf2: Microsemi Smartfusion2 System Register block", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e458ea9f9cbb22dd84056ffbe1d70f73a1254a3e", "submitter": { "id": 64324, "url": "http://patchwork.ozlabs.org/api/people/64324/?format=api", "name": "sundeep subbaraya", "email": "sundeep.lkml@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505494753-10837-3-git-send-email-sundeep.lkml@gmail.com/mbox/", "series": [ { "id": 3336, "url": "http://patchwork.ozlabs.org/api/series/3336/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=3336", "date": "2017-09-15T16:59:10", "name": "Add support for Smartfusion2 SoC", "version": 9, "mbox": "http://patchwork.ozlabs.org/series/3336/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/814329/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/814329/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) 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([2001:4830:134:3::10]:49894)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <sundeep.lkml@gmail.com>) id 1dstxo-0005Lh-0q\n\tfor qemu-devel@nongnu.org; Fri, 15 Sep 2017 12:59:37 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <sundeep.lkml@gmail.com>) id 1dstxm-00040o-AZ\n\tfor qemu-devel@nongnu.org; Fri, 15 Sep 2017 12:59:36 -0400", "from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:37155)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <sundeep.lkml@gmail.com>)\n\tid 1dstxm-00040S-1U; Fri, 15 Sep 2017 12:59:34 -0400", "by mail-pg0-x241.google.com with SMTP id v5so1604506pgn.4;\n\tFri, 15 Sep 2017 09:59:33 -0700 (PDT)", "from localhost.localdomain ([124.123.70.3])\n\tby smtp.gmail.com with ESMTPSA id\n\ts17sm3111350pgq.25.2017.09.15.09.59.30\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tFri, 15 Sep 2017 09:59:32 -0700 (PDT)" ], "DKIM-Signature": "v=1; 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s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=1WAwVPtpZXqZZ15+91n4L5JPOoERq2cMzHEIWB+S184=;\n\tb=b3VChdt7z7K1Jvp6RX4PLUWoK+XFpZi6W/lQlyw9ZUfJ1rkAMtMsrPe7A84LJ2bXL0\n\tUcJPBW1V3Eaqtk/lVQdwrrKa/QKXuPiVmy32OCBmW2vOUJzRHbPrDoNEfMSX6kYmwJB9\n\tf3hS1j3RgQdecC2zO948POLANy/fNuqs3A/Ol/XFo1JQ2AtbLcGBFuign6BSbseo+Qy6\n\teRE1pFvk3o/4JFQ9WSEo6rO1+G/uXnsW/TMa4DSJ6Z9EN7uPBe2t8aqZttryKw+wjgGq\n\t/wg0F6ZIZqjocoqzEBAxNQZ73lnTuMRRXwVuhd7A4zSevXqtiOSuIvTFzEGFJBamQC9H\n\tMKNA==", "X-Gm-Message-State": "AHPjjUhyFPcq+wYB28ZkKcLoncNWDpElqgzDCsEtP0rbiIkvPZyy2kCv\n\tLSXkKjXu6py8PRWu", "X-Google-Smtp-Source": "ADKCNb6Et92bB5Biv793pKprQSCacJ8Lb+kGr2tvAmDsiCxwLfq3j6RkWy/sF2bS+CYggJTiKbB2Gg==", "X-Received": "by 10.98.62.93 with SMTP id l90mr25228765pfa.32.1505494772858;\n\tFri, 15 Sep 2017 09:59:32 -0700 (PDT)", "From": "Subbaraya Sundeep <sundeep.lkml@gmail.com>", "To": "qemu-devel@nongnu.org,\n\tqemu-arm@nongnu.org", "Date": "Fri, 15 Sep 2017 22:29:10 +0530", "Message-Id": "<1505494753-10837-3-git-send-email-sundeep.lkml@gmail.com>", "X-Mailer": "git-send-email 2.5.0", "In-Reply-To": "<1505494753-10837-1-git-send-email-sundeep.lkml@gmail.com>", "References": "<1505494753-10837-1-git-send-email-sundeep.lkml@gmail.com>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::241", "Subject": "[Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi Smartfusion2\n\tSystem Register block", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Subbaraya Sundeep <sundeep.lkml@gmail.com>,\n\tf4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Added Sytem register block of Smartfusion2.\nThis block has PLL registers which are accessed by guest.\n\nSigned-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com>\nReviewed-by: Alistair Francis <alistair.francis@xilinx.com>\n---\n hw/misc/Makefile.objs | 1 +\n hw/misc/msf2-sysreg.c | 168 ++++++++++++++++++++++++++++++++++++++++++\n hw/misc/trace-events | 5 ++\n include/hw/misc/msf2-sysreg.h | 77 +++++++++++++++++++\n 4 files changed, 251 insertions(+)\n create mode 100644 hw/misc/msf2-sysreg.c\n create mode 100644 include/hw/misc/msf2-sysreg.h", "diff": "diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs\nindex 29fb922..e8f0a02 100644\n--- a/hw/misc/Makefile.objs\n+++ b/hw/misc/Makefile.objs\n@@ -59,3 +59,4 @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o\n obj-$(CONFIG_AUX) += auxbus.o\n obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o\n obj-y += mmio_interface.o\n+obj-$(CONFIG_MSF2) += msf2-sysreg.o\ndiff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c\nnew file mode 100644\nindex 0000000..dc3597b\n--- /dev/null\n+++ b/hw/misc/msf2-sysreg.c\n@@ -0,0 +1,168 @@\n+/*\n+ * System Register block model of Microsemi SmartFusion2.\n+ *\n+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>\n+ *\n+ * This program is free software; you can redistribute it and/or\n+ * modify it under the terms of the GNU General Public License\n+ * as published by the Free Software Foundation; either version\n+ * 2 of the License, or (at your option) any later version.\n+ *\n+ * You should have received a copy of the GNU General Public License along\n+ * with this program; if not, see <http://www.gnu.org/licenses/>.\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"qemu/log.h\"\n+#include \"hw/misc/msf2-sysreg.h\"\n+#include \"trace.h\"\n+\n+static inline int msf2_divbits(uint32_t div)\n+{\n+ int ret = 0;\n+\n+ switch (div) {\n+ case 1:\n+ ret = 0;\n+ break;\n+ case 2:\n+ ret = 1;\n+ break;\n+ case 4:\n+ ret = 2;\n+ break;\n+ case 8:\n+ ret = 4;\n+ break;\n+ case 16:\n+ ret = 5;\n+ break;\n+ case 32:\n+ ret = 6;\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ return ret;\n+}\n+\n+static void msf2_sysreg_reset(DeviceState *d)\n+{\n+ MSF2SysregState *s = MSF2_SYSREG(d);\n+\n+ s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;\n+ s->regs[MSSDDR_PLL_STATUS] = 0x3;\n+ s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |\n+ msf2_divbits(s->apb1div) << 2;\n+}\n+\n+static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,\n+ unsigned size)\n+{\n+ MSF2SysregState *s = opaque;\n+ uint32_t ret = 0;\n+\n+ offset >>= 2;\n+ if (offset < ARRAY_SIZE(s->regs)) {\n+ ret = s->regs[offset];\n+ trace_msf2_sysreg_read(offset << 2, ret);\n+ } else {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"%s: Bad offset 0x%08\" HWADDR_PRIx \"\\n\", __func__,\n+ offset << 2);\n+ }\n+\n+ return ret;\n+}\n+\n+static void msf2_sysreg_write(void *opaque, hwaddr offset,\n+ uint64_t val, unsigned size)\n+{\n+ MSF2SysregState *s = opaque;\n+ uint32_t newval = val;\n+\n+ offset >>= 2;\n+\n+ switch (offset) {\n+ case MSSDDR_PLL_STATUS:\n+ trace_msf2_sysreg_write_pll_status();\n+ break;\n+\n+ case ESRAM_CR:\n+ case DDR_CR:\n+ case ENVM_REMAP_BASE_CR:\n+ if (newval != s->regs[offset]) {\n+ qemu_log_mask(LOG_UNIMP,\n+ TYPE_MSF2_SYSREG\": remapping not supported\\n\");\n+ }\n+ break;\n+\n+ default:\n+ if (offset < ARRAY_SIZE(s->regs)) {\n+ trace_msf2_sysreg_write(offset << 2, newval, s->regs[offset]);\n+ s->regs[offset] = newval;\n+ } else {\n+ qemu_log_mask(LOG_GUEST_ERROR,\n+ \"%s: Bad offset 0x%08\" HWADDR_PRIx \"\\n\", __func__,\n+ offset << 2);\n+ }\n+ break;\n+ }\n+}\n+\n+static const MemoryRegionOps sysreg_ops = {\n+ .read = msf2_sysreg_read,\n+ .write = msf2_sysreg_write,\n+ .endianness = DEVICE_NATIVE_ENDIAN,\n+};\n+\n+static void msf2_sysreg_init(Object *obj)\n+{\n+ MSF2SysregState *s = MSF2_SYSREG(obj);\n+\n+ memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG,\n+ MSF2_SYSREG_MMIO_SIZE);\n+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);\n+}\n+\n+static const VMStateDescription vmstate_msf2_sysreg = {\n+ .name = TYPE_MSF2_SYSREG,\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_MMIO_SIZE / 4),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n+static Property msf2_sysreg_properties[] = {\n+ /* default divisors in Libero GUI */\n+ DEFINE_PROP_UINT32(\"apb0divisor\", MSF2SysregState, apb0div, 2),\n+ DEFINE_PROP_UINT32(\"apb1divisor\", MSF2SysregState, apb1div, 2),\n+ DEFINE_PROP_END_OF_LIST(),\n+};\n+\n+static void msf2_sysreg_class_init(ObjectClass *klass, void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+\n+ dc->vmsd = &vmstate_msf2_sysreg;\n+ dc->reset = msf2_sysreg_reset;\n+ dc->props = msf2_sysreg_properties;\n+}\n+\n+static const TypeInfo msf2_sysreg_info = {\n+ .name = TYPE_MSF2_SYSREG,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .class_init = msf2_sysreg_class_init,\n+ .instance_size = sizeof(MSF2SysregState),\n+ .instance_init = msf2_sysreg_init,\n+};\n+\n+static void msf2_sysreg_register_types(void)\n+{\n+ type_register_static(&msf2_sysreg_info);\n+}\n+\n+type_init(msf2_sysreg_register_types)\ndiff --git a/hw/misc/trace-events b/hw/misc/trace-events\nindex 3313585..616579a 100644\n--- a/hw/misc/trace-events\n+++ b/hw/misc/trace-events\n@@ -61,3 +61,8 @@ mps2_scc_reset(void) \"MPS2 SCC: reset\"\n mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2, char led1, char led0) \"MPS2 SCC LEDs: %c%c%c%c%c%c%c%c\"\n mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) \"MPS2 SCC config write: function %d device %d data 0x%\" PRIx32\n mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) \"MPS2 SCC config read: function %d device %d data 0x%\" PRIx32\n+\n+# hw/misc/msf2-sysreg.c\n+msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) \"msf2-sysreg write: addr 0x%08\" HWADDR_PRIx \" data 0x%\" PRIx32 \" prev 0x%\" PRIx32\n+msf2_sysreg_read(uint64_t offset, uint32_t val) \"msf2-sysreg read: addr 0x%08\" HWADDR_PRIx \" data 0x%08\" PRIx32\n+msf2_sysreg_write_pll_status(void) \"Invalid write to read only PLL status register\"\ndiff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h\nnew file mode 100644\nindex 0000000..231f827\n--- /dev/null\n+++ b/include/hw/misc/msf2-sysreg.h\n@@ -0,0 +1,77 @@\n+/*\n+ * Microsemi SmartFusion2 SYSREG\n+ *\n+ * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>\n+ *\n+ * Permission is hereby granted, free of charge, to any person obtaining a copy\n+ * of this software and associated documentation files (the \"Software\"), to deal\n+ * in the Software without restriction, including without limitation the rights\n+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n+ * copies of the Software, and to permit persons to whom the Software is\n+ * furnished to do so, subject to the following conditions:\n+ *\n+ * The above copyright notice and this permission notice shall be included in\n+ * all copies or substantial portions of the Software.\n+ *\n+ * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n+ * THE SOFTWARE.\n+ */\n+\n+#ifndef HW_MSF2_SYSREG_H\n+#define HW_MSF2_SYSREG_H\n+\n+#include \"hw/sysbus.h\"\n+\n+enum {\n+ ESRAM_CR = 0x00 / 4,\n+ ESRAM_MAX_LAT,\n+ DDR_CR,\n+ ENVM_CR,\n+ ENVM_REMAP_BASE_CR,\n+ ENVM_REMAP_FAB_CR,\n+ CC_CR,\n+ CC_REGION_CR,\n+ CC_LOCK_BASE_ADDR_CR,\n+ CC_FLUSH_INDX_CR,\n+ DDRB_BUF_TIMER_CR,\n+ DDRB_NB_ADDR_CR,\n+ DDRB_NB_SIZE_CR,\n+ DDRB_CR,\n+\n+ SOFT_RESET_CR = 0x48 / 4,\n+ M3_CR,\n+\n+ GPIO_SYSRESET_SEL_CR = 0x58 / 4,\n+\n+ MDDR_CR = 0x60 / 4,\n+\n+ MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,\n+ MSSDDR_PLL_STATUS_HIGH_CR,\n+ MSSDDR_FACC1_CR,\n+ MSSDDR_FACC2_CR,\n+\n+ MSSDDR_PLL_STATUS = 0x150 / 4,\n+};\n+\n+#define MSF2_SYSREG_MMIO_SIZE 0x300\n+\n+#define TYPE_MSF2_SYSREG \"msf2-sysreg\"\n+#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG)\n+\n+typedef struct MSF2SysregState {\n+ SysBusDevice parent_obj;\n+\n+ MemoryRegion iomem;\n+\n+ uint32_t apb0div;\n+ uint32_t apb1div;\n+\n+ uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4];\n+} MSF2SysregState;\n+\n+#endif /* HW_MSF2_SYSREG_H */\n", "prefixes": [ "Qemu", "devel", "v9", "2/5" ] }