[{"id":1769826,"web_url":"http://patchwork.ozlabs.org/comment/1769826/","msgid":"<2c6a4136-fb80-2000-940c-1df5e718cbf1@amsat.org>","list_archive_url":null,"date":"2017-09-18T01:01:56","subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"Hi Sundeep, Peter,\n\nOn 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:\n> Added Sytem register block of Smartfusion2.\n> This block has PLL registers which are accessed by guest.\n> \n> Signed-off-by: Subbaraya Sundeep \n> Reviewed-by: Alistair Francis \n> ---\n> hw/misc/Makefile.objs | 1 +\n> hw/misc/msf2-sysreg.c | 168 ++++++++++++++++++++++++++++++++++++++++++\n> hw/misc/trace-events | 5 ++\n> include/hw/misc/msf2-sysreg.h | 77 +++++++++++++++++++\n> 4 files changed, 251 insertions(+)\n> create mode 100644 hw/misc/msf2-sysreg.c\n> create mode 100644 include/hw/misc/msf2-sysreg.h\n> \n> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs\n> index 29fb922..e8f0a02 100644\n> --- a/hw/misc/Makefile.objs\n> +++ b/hw/misc/Makefile.objs\n> @@ -59,3 +59,4 @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o\n> obj-$(CONFIG_AUX) += auxbus.o\n> obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o\n> obj-y += mmio_interface.o\n> +obj-$(CONFIG_MSF2) += msf2-sysreg.o\n> diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c\n> new file mode 100644\n> index 0000000..dc3597b\n> --- /dev/null\n> +++ b/hw/misc/msf2-sysreg.c\n> @@ -0,0 +1,168 @@\n> +/*\n> + * System Register block model of Microsemi SmartFusion2.\n> + *\n> + * Copyright (c) 2017 Subbaraya Sundeep \n> + *\n> + * This program is free software; you can redistribute it and/or\n> + * modify it under the terms of the GNU General Public License\n> + * as published by the Free Software Foundation; either version\n> + * 2 of the License, or (at your option) any later version.\n> + *\n> + * You should have received a copy of the GNU General Public License along\n> + * with this program; if not, see .\n> + */\n> +\n> +#include \"qemu/osdep.h\"\n> +#include \"qemu/log.h\"\n> +#include \"hw/misc/msf2-sysreg.h\"\n> +#include \"trace.h\"\n> +\n> +static inline int msf2_divbits(uint32_t div)\n> +{\n> + int ret = 0;\n> +\n> + switch (div) {\n> + case 1:\n> + ret = 0;\n> + break;\n> + case 2:\n> + ret = 1;\n> + break;\n> + case 4:\n> + ret = 2;\n> + break;\n> + case 8:\n> + ret = 4;\n> + break;\n> + case 16:\n> + ret = 5;\n> + break;\n> + case 32:\n> + ret = 6;\n> + break;\n> + default:\n> + break;\n\neh?\n\n> + }\n> +\n> + return ret;\n> +}\n> +\n> +static void msf2_sysreg_reset(DeviceState *d)\n> +{\n> + MSF2SysregState *s = MSF2_SYSREG(d);\n> +\n> + s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;\n> + s->regs[MSSDDR_PLL_STATUS] = 0x3;\n> + s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |\n\nctz32(s->apb0div) << 5 ...\n\n> + msf2_divbits(s->apb1div) << 2;\n> +}\n> +\n> +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,\n> + unsigned size)\n> +{\n> + MSF2SysregState *s = opaque;\n> + uint32_t ret = 0;\n> +\n> + offset >>= 2;\n> + if (offset < ARRAY_SIZE(s->regs)) {\n> + ret = s->regs[offset];\n> + trace_msf2_sysreg_read(offset << 2, ret);\n> + } else {\n> + qemu_log_mask(LOG_GUEST_ERROR,\n> + \"%s: Bad offset 0x%08\" HWADDR_PRIx \"\\n\", __func__,\n> + offset << 2);\n> + }\n> +\n> + return ret;\n> +}\n> +\n> +static void msf2_sysreg_write(void *opaque, hwaddr offset,\n> + uint64_t val, unsigned size)\n> +{\n> + MSF2SysregState *s = opaque;\n> + uint32_t newval = val;\n> +\n> + offset >>= 2;\n> +\n> + switch (offset) {\n> + case MSSDDR_PLL_STATUS:\n> + trace_msf2_sysreg_write_pll_status();\n> + break;\n> +\n> + case ESRAM_CR:\n> + case DDR_CR:\n> + case ENVM_REMAP_BASE_CR:\n> + if (newval != s->regs[offset]) {\n> + qemu_log_mask(LOG_UNIMP,\n> + TYPE_MSF2_SYSREG\": remapping not supported\\n\");\n\nI'd rather exit here than continue with inconsistent cpu, Peter what do \nyou recommend?\n\n> + }\n> + break;\n> +\n> + default:\n> + if (offset < ARRAY_SIZE(s->regs)) {\n> + trace_msf2_sysreg_write(offset << 2, newval, s->regs[offset]);\n> + s->regs[offset] = newval;\n> + } else {\n> + qemu_log_mask(LOG_GUEST_ERROR,\n> + \"%s: Bad offset 0x%08\" HWADDR_PRIx \"\\n\", __func__,\n> + offset << 2);\n> + }\n> + break;\n> + }\n> +}\n> +\n> +static const MemoryRegionOps sysreg_ops = {\n> + .read = msf2_sysreg_read,\n> + .write = msf2_sysreg_write,\n> + .endianness = DEVICE_NATIVE_ENDIAN,\n> +};\n> +\n> +static void msf2_sysreg_init(Object *obj)\n> +{\n> + MSF2SysregState *s = MSF2_SYSREG(obj);\n> +\n> + memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG,\n> + MSF2_SYSREG_MMIO_SIZE);\n> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);\n> +}\n> +\n> +static const VMStateDescription vmstate_msf2_sysreg = {\n> + .name = TYPE_MSF2_SYSREG,\n> + .version_id = 1,\n> + .minimum_version_id = 1,\n> + .fields = (VMStateField[]) {\n> + VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_MMIO_SIZE / 4),\n> + VMSTATE_END_OF_LIST()\n> + }\n> +};\n> +\n> +static Property msf2_sysreg_properties[] = {\n> + /* default divisors in Libero GUI */\n> + DEFINE_PROP_UINT32(\"apb0divisor\", MSF2SysregState, apb0div, 2),\n> + DEFINE_PROP_UINT32(\"apb1divisor\", MSF2SysregState, apb1div, 2),\n\nDEFINE_PROP_UINT8() is enough for both.\n\nBeware these divisors must be power of 2, and maximum 32.\n\nThis can be checked in msf2_sysreg_realize() ...\n\n> + DEFINE_PROP_END_OF_LIST(),\n> +};\n> +\n> +static void msf2_sysreg_class_init(ObjectClass *klass, void *data)\n> +{\n> + DeviceClass *dc = DEVICE_CLASS(klass);\n> +\n> + dc->vmsd = &vmstate_msf2_sysreg;\n> + dc->reset = msf2_sysreg_reset;\n\n... which would go here:\n\n dc->realize = msf2_sysreg_realize;\n\n> + dc->props = msf2_sysreg_properties;\n> +}\n> +\n> +static const TypeInfo msf2_sysreg_info = {\n> + .name = TYPE_MSF2_SYSREG,\n> + .parent = TYPE_SYS_BUS_DEVICE,\n> + .class_init = msf2_sysreg_class_init,\n> + .instance_size = sizeof(MSF2SysregState),\n> + .instance_init = msf2_sysreg_init,\n> +};\n> +\n> +static void msf2_sysreg_register_types(void)\n> +{\n> + type_register_static(&msf2_sysreg_info);\n> +}\n> +\n> +type_init(msf2_sysreg_register_types)\n> diff --git a/hw/misc/trace-events b/hw/misc/trace-events\n> index 3313585..616579a 100644\n> --- a/hw/misc/trace-events\n> +++ b/hw/misc/trace-events\n> @@ -61,3 +61,8 @@ mps2_scc_reset(void) \"MPS2 SCC: reset\"\n> mps2_scc_leds(char led7, char led6, char led5, char led4, char led3, char led2, char led1, char led0) \"MPS2 SCC LEDs: %c%c%c%c%c%c%c%c\"\n> mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value) \"MPS2 SCC config write: function %d device %d data 0x%\" PRIx32\n> mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value) \"MPS2 SCC config read: function %d device %d data 0x%\" PRIx32\n> +\n> +# hw/misc/msf2-sysreg.c\n> +msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev) \"msf2-sysreg write: addr 0x%08\" HWADDR_PRIx \" data 0x%\" PRIx32 \" prev 0x%\" PRIx32\n> +msf2_sysreg_read(uint64_t offset, uint32_t val) \"msf2-sysreg read: addr 0x%08\" HWADDR_PRIx \" data 0x%08\" PRIx32\n> +msf2_sysreg_write_pll_status(void) \"Invalid write to read only PLL status register\"\n> diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h\n> new file mode 100644\n> index 0000000..231f827\n> --- /dev/null\n> +++ b/include/hw/misc/msf2-sysreg.h\n> @@ -0,0 +1,77 @@\n> +/*\n> + * Microsemi SmartFusion2 SYSREG\n> + *\n> + * Copyright (c) 2017 Subbaraya Sundeep \n> + *\n> + * Permission is hereby granted, free of charge, to any person obtaining a copy\n> + * of this software and associated documentation files (the \"Software\"), to deal\n> + * in the Software without restriction, including without limitation the rights\n> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell\n> + * copies of the Software, and to permit persons to whom the Software is\n> + * furnished to do so, subject to the following conditions:\n> + *\n> + * The above copyright notice and this permission notice shall be included in\n> + * all copies or substantial portions of the Software.\n> + *\n> + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\n> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\n> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\n> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER\n> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,\n> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN\n> + * THE SOFTWARE.\n> + */\n> +\n> +#ifndef HW_MSF2_SYSREG_H\n> +#define HW_MSF2_SYSREG_H\n> +\n> +#include \"hw/sysbus.h\"\n> +\n> +enum {\n> + ESRAM_CR = 0x00 / 4,\n> + ESRAM_MAX_LAT,\n> + DDR_CR,\n> + ENVM_CR,\n> + ENVM_REMAP_BASE_CR,\n> + ENVM_REMAP_FAB_CR,\n> + CC_CR,\n> + CC_REGION_CR,\n> + CC_LOCK_BASE_ADDR_CR,\n> + CC_FLUSH_INDX_CR,\n> + DDRB_BUF_TIMER_CR,\n> + DDRB_NB_ADDR_CR,\n> + DDRB_NB_SIZE_CR,\n> + DDRB_CR,\n> +\n> + SOFT_RESET_CR = 0x48 / 4,\n> + M3_CR,\n> +\n> + GPIO_SYSRESET_SEL_CR = 0x58 / 4,\n> +\n> + MDDR_CR = 0x60 / 4,\n> +\n> + MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,\n> + MSSDDR_PLL_STATUS_HIGH_CR,\n> + MSSDDR_FACC1_CR,\n> + MSSDDR_FACC2_CR,\n> +\n> + MSSDDR_PLL_STATUS = 0x150 / 4,\n> +};\n> +\n> +#define MSF2_SYSREG_MMIO_SIZE 0x300\n> +\n> +#define TYPE_MSF2_SYSREG \"msf2-sysreg\"\n> +#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_SYSREG)\n> +\n> +typedef struct MSF2SysregState {\n> + SysBusDevice parent_obj;\n> +\n> + MemoryRegion iomem;\n> +\n> + uint32_t apb0div;\n> + uint32_t apb1div;\n\nuint8_t for both\n\n> +\n> + uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4];\n> +} MSF2SysregState;\n> +\n> +#endif /* HW_MSF2_SYSREG_H */\n> \n\nAcked-by: Philippe Mathieu-Daudé \nTested-by: Philippe Mathieu-Daudé ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) 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","References":"<1505494753-10837-1-git-send-email-sundeep.lkml@gmail.com>\n\t<1505494753-10837-3-git-send-email-sundeep.lkml@gmail.com>","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Message-ID":"<2c6a4136-fb80-2000-940c-1df5e718cbf1@amsat.org>","Date":"Sun, 17 Sep 2017 22:01:56 -0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1505494753-10837-3-git-send-email-sundeep.lkml@gmail.com>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::243","Subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org,\n\talistair23@gmail.com, crosthwaite.peter@gmail.com","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1770055,"web_url":"http://patchwork.ozlabs.org/comment/1770055/","msgid":"","list_archive_url":null,"date":"2017-09-18T10:17:52","subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","submitter":{"id":64324,"url":"http://patchwork.ozlabs.org/api/people/64324/","name":"sundeep subbaraya","email":"sundeep.lkml@gmail.com"},"content":"Hi Philippe,\n\nOn Mon, Sep 18, 2017 at 6:31 AM, Philippe Mathieu-Daudé \nwrote:\n\n> Hi Sundeep, Peter,\n>\n>\n> On 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:\n>\n>> Added Sytem register block of Smartfusion2.\n>> This block has PLL registers which are accessed by guest.\n>>\n>> Signed-off-by: Subbaraya Sundeep \n>> Reviewed-by: Alistair Francis \n>> ---\n>> hw/misc/Makefile.objs | 1 +\n>> hw/misc/msf2-sysreg.c | 168 ++++++++++++++++++++++++++++++\n>> ++++++++++++\n>> hw/misc/trace-events | 5 ++\n>> include/hw/misc/msf2-sysreg.h | 77 +++++++++++++++++++\n>> 4 files changed, 251 insertions(+)\n>> create mode 100644 hw/misc/msf2-sysreg.c\n>> create mode 100644 include/hw/misc/msf2-sysreg.h\n>>\n>> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs\n>> index 29fb922..e8f0a02 100644\n>> --- a/hw/misc/Makefile.objs\n>> +++ b/hw/misc/Makefile.objs\n>> @@ -59,3 +59,4 @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o\n>> obj-$(CONFIG_AUX) += auxbus.o\n>> obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o\n>> obj-y += mmio_interface.o\n>> +obj-$(CONFIG_MSF2) += msf2-sysreg.o\n>> diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c\n>> new file mode 100644\n>> index 0000000..dc3597b\n>> --- /dev/null\n>> +++ b/hw/misc/msf2-sysreg.c\n>> @@ -0,0 +1,168 @@\n>> +/*\n>> + * System Register block model of Microsemi SmartFusion2.\n>> + *\n>> + * Copyright (c) 2017 Subbaraya Sundeep \n>> + *\n>> + * This program is free software; you can redistribute it and/or\n>> + * modify it under the terms of the GNU General Public License\n>> + * as published by the Free Software Foundation; either version\n>> + * 2 of the License, or (at your option) any later version.\n>> + *\n>> + * You should have received a copy of the GNU General Public License\n>> along\n>> + * with this program; if not, see .\n>> + */\n>> +\n>> +#include \"qemu/osdep.h\"\n>> +#include \"qemu/log.h\"\n>> +#include \"hw/misc/msf2-sysreg.h\"\n>> +#include \"trace.h\"\n>> +\n>> +static inline int msf2_divbits(uint32_t div)\n>> +{\n>> + int ret = 0;\n>> +\n>> + switch (div) {\n>> + case 1:\n>> + ret = 0;\n>> + break;\n>> + case 2:\n>> + ret = 1;\n>> + break;\n>> + case 4:\n>> + ret = 2;\n>> + break;\n>> + case 8:\n>> + ret = 4;\n>> + break;\n>> + case 16:\n>> + ret = 5;\n>> + break;\n>> + case 32:\n>> + ret = 6;\n>> + break;\n>> + default:\n>> + break;\n>>\n>\n> eh?\n>\n> + }\n>> +\n>> + return ret;\n>> +}\n>> +\n>> +static void msf2_sysreg_reset(DeviceState *d)\n>> +{\n>> + MSF2SysregState *s = MSF2_SYSREG(d);\n>> +\n>> + s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;\n>> + s->regs[MSSDDR_PLL_STATUS] = 0x3;\n>> + s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |\n>>\n>\n> ctz32(s->apb0div) << 5 ...\n\n\nI will modify like below:\ndiv0 = s->apb0div < 8 ? ctz32(s->apb0div) : ctz32(s->apb0div) + 1;\ndiv1 = s->apb1div < 8 ? ctz32(s->apb1div) : ctz32(s->apb1div) + 1;\ns->regs[MSSDDR_FACC1_CR] = div0 << 5 | div1 << 2;\n\n\n>\n> + msf2_divbits(s->apb1div) << 2;\n>> +}\n>> +\n>> +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,\n>> + unsigned size)\n>> +{\n>> + MSF2SysregState *s = opaque;\n>> + uint32_t ret = 0;\n>> +\n>> + offset >>= 2;\n>> + if (offset < ARRAY_SIZE(s->regs)) {\n>> + ret = s->regs[offset];\n>> + trace_msf2_sysreg_read(offset << 2, ret);\n>> + } else {\n>> + qemu_log_mask(LOG_GUEST_ERROR,\n>> + \"%s: Bad offset 0x%08\" HWADDR_PRIx \"\\n\", __func__,\n>> + offset << 2);\n>> + }\n>> +\n>> + return ret;\n>> +}\n>> +\n>> +static void msf2_sysreg_write(void *opaque, hwaddr offset,\n>> + uint64_t val, unsigned size)\n>> +{\n>> + MSF2SysregState *s = opaque;\n>> + uint32_t newval = val;\n>> +\n>> + offset >>= 2;\n>> +\n>> + switch (offset) {\n>> + case MSSDDR_PLL_STATUS:\n>> + trace_msf2_sysreg_write_pll_status();\n>> + break;\n>> +\n>> + case ESRAM_CR:\n>> + case DDR_CR:\n>> + case ENVM_REMAP_BASE_CR:\n>> + if (newval != s->regs[offset]) {\n>> + qemu_log_mask(LOG_UNIMP,\n>> + TYPE_MSF2_SYSREG\": remapping not supported\\n\");\n>>\n>\n> I'd rather exit here than continue with inconsistent cpu, Peter what do\n> you recommend?\n>\n>\n> + }\n>> + break;\n>> +\n>> + default:\n>> + if (offset < ARRAY_SIZE(s->regs)) {\n>> + trace_msf2_sysreg_write(offset << 2, newval,\n>> s->regs[offset]);\n>> + s->regs[offset] = newval;\n>> + } else {\n>> + qemu_log_mask(LOG_GUEST_ERROR,\n>> + \"%s: Bad offset 0x%08\" HWADDR_PRIx \"\\n\",\n>> __func__,\n>> + offset << 2);\n>> + }\n>> + break;\n>> + }\n>> +}\n>> +\n>> +static const MemoryRegionOps sysreg_ops = {\n>> + .read = msf2_sysreg_read,\n>> + .write = msf2_sysreg_write,\n>> + .endianness = DEVICE_NATIVE_ENDIAN,\n>> +};\n>> +\n>> +static void msf2_sysreg_init(Object *obj)\n>> +{\n>> + MSF2SysregState *s = MSF2_SYSREG(obj);\n>> +\n>> + memory_region_init_io(&s->iomem, obj, &sysreg_ops, s,\n>> TYPE_MSF2_SYSREG,\n>> + MSF2_SYSREG_MMIO_SIZE);\n>> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);\n>> +}\n>> +\n>> +static const VMStateDescription vmstate_msf2_sysreg = {\n>> + .name = TYPE_MSF2_SYSREG,\n>> + .version_id = 1,\n>> + .minimum_version_id = 1,\n>> + .fields = (VMStateField[]) {\n>> + VMSTATE_UINT32_ARRAY(regs, MSF2SysregState,\n>> MSF2_SYSREG_MMIO_SIZE / 4),\n>> + VMSTATE_END_OF_LIST()\n>> + }\n>> +};\n>> +\n>> +static Property msf2_sysreg_properties[] = {\n>> + /* default divisors in Libero GUI */\n>> + DEFINE_PROP_UINT32(\"apb0divisor\", MSF2SysregState, apb0div, 2),\n>> + DEFINE_PROP_UINT32(\"apb1divisor\", MSF2SysregState, apb1div, 2),\n>>\n>\n> DEFINE_PROP_UINT8() is enough for both.\n>\n> Beware these divisors must be power of 2, and maximum 32.\n\nThis can be checked in msf2_sysreg_realize() ...\n\n\nOk\n\n>\n>\n> + DEFINE_PROP_END_OF_LIST(),\n>> +};\n>> +\n>> +static void msf2_sysreg_class_init(ObjectClass *klass, void *data)\n>> +{\n>> + DeviceClass *dc = DEVICE_CLASS(klass);\n>> +\n>> + dc->vmsd = &vmstate_msf2_sysreg;\n>> + dc->reset = msf2_sysreg_reset;\n>>\n>\n> ... which would go here:\n>\n> dc->realize = msf2_sysreg_realize;\n>\n> Ok.\n\n>\n> + dc->props = msf2_sysreg_properties;\n>> +}\n>> +\n>> +static const TypeInfo msf2_sysreg_info = {\n>> + .name = TYPE_MSF2_SYSREG,\n>> + .parent = TYPE_SYS_BUS_DEVICE,\n>> + .class_init = msf2_sysreg_class_init,\n>> + .instance_size = sizeof(MSF2SysregState),\n>> + .instance_init = msf2_sysreg_init,\n>> +};\n>> +\n>> +static void msf2_sysreg_register_types(void)\n>> +{\n>> + type_register_static(&msf2_sysreg_info);\n>> +}\n>> +\n>> +type_init(msf2_sysreg_register_types)\n>> diff --git a/hw/misc/trace-events b/hw/misc/trace-events\n>> index 3313585..616579a 100644\n>> --- a/hw/misc/trace-events\n>> +++ b/hw/misc/trace-events\n>> @@ -61,3 +61,8 @@ mps2_scc_reset(void) \"MPS2 SCC: reset\"\n>> mps2_scc_leds(char led7, char led6, char led5, char led4, char led3,\n>> char led2, char led1, char led0) \"MPS2 SCC LEDs: %c%c%c%c%c%c%c%c\"\n>> mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value)\n>> \"MPS2 SCC config write: function %d device %d data 0x%\" PRIx32\n>> mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value)\n>> \"MPS2 SCC config read: function %d device %d data 0x%\" PRIx32\n>> +\n>> +# hw/misc/msf2-sysreg.c\n>> +msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev)\n>> \"msf2-sysreg write: addr 0x%08\" HWADDR_PRIx \" data 0x%\" PRIx32 \" prev 0x%\"\n>> PRIx32\n>> +msf2_sysreg_read(uint64_t offset, uint32_t val) \"msf2-sysreg read: addr\n>> 0x%08\" HWADDR_PRIx \" data 0x%08\" PRIx32\n>> +msf2_sysreg_write_pll_status(void) \"Invalid write to read only PLL\n>> status register\"\n>> diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.\n>> h\n>> new file mode 100644\n>> index 0000000..231f827\n>> --- /dev/null\n>> +++ b/include/hw/misc/msf2-sysreg.h\n>> @@ -0,0 +1,77 @@\n>> +/*\n>> + * Microsemi SmartFusion2 SYSREG\n>> + *\n>> + * Copyright (c) 2017 Subbaraya Sundeep \n>> + *\n>> + * Permission is hereby granted, free of charge, to any person obtaining\n>> a copy\n>> + * of this software and associated documentation files (the \"Software\"),\n>> to deal\n>> + * in the Software without restriction, including without limitation the\n>> rights\n>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or\n>> sell\n>> + * copies of the Software, and to permit persons to whom the Software is\n>> + * furnished to do so, subject to the following conditions:\n>> + *\n>> + * The above copyright notice and this permission notice shall be\n>> included in\n>> + * all copies or substantial portions of the Software.\n>> + *\n>> + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n>> EXPRESS OR\n>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n>> MERCHANTABILITY,\n>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT\n>> SHALL\n>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR\n>> OTHER\n>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,\n>> ARISING FROM,\n>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n>> DEALINGS IN\n>> + * THE SOFTWARE.\n>> + */\n>> +\n>> +#ifndef HW_MSF2_SYSREG_H\n>> +#define HW_MSF2_SYSREG_H\n>> +\n>> +#include \"hw/sysbus.h\"\n>> +\n>> +enum {\n>> + ESRAM_CR = 0x00 / 4,\n>> + ESRAM_MAX_LAT,\n>> + DDR_CR,\n>> + ENVM_CR,\n>> + ENVM_REMAP_BASE_CR,\n>> + ENVM_REMAP_FAB_CR,\n>> + CC_CR,\n>> + CC_REGION_CR,\n>> + CC_LOCK_BASE_ADDR_CR,\n>> + CC_FLUSH_INDX_CR,\n>> + DDRB_BUF_TIMER_CR,\n>> + DDRB_NB_ADDR_CR,\n>> + DDRB_NB_SIZE_CR,\n>> + DDRB_CR,\n>> +\n>> + SOFT_RESET_CR = 0x48 / 4,\n>> + M3_CR,\n>> +\n>> + GPIO_SYSRESET_SEL_CR = 0x58 / 4,\n>> +\n>> + MDDR_CR = 0x60 / 4,\n>> +\n>> + MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,\n>> + MSSDDR_PLL_STATUS_HIGH_CR,\n>> + MSSDDR_FACC1_CR,\n>> + MSSDDR_FACC2_CR,\n>> +\n>> + MSSDDR_PLL_STATUS = 0x150 / 4,\n>> +};\n>> +\n>> +#define MSF2_SYSREG_MMIO_SIZE 0x300\n>> +\n>> +#define TYPE_MSF2_SYSREG \"msf2-sysreg\"\n>> +#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj),\n>> TYPE_MSF2_SYSREG)\n>> +\n>> +typedef struct MSF2SysregState {\n>> + SysBusDevice parent_obj;\n>> +\n>> + MemoryRegion iomem;\n>> +\n>> + uint32_t apb0div;\n>> + uint32_t apb1div;\n>>\n>\n> uint8_t for both\n\n\nOk.\n\n>\n>\n> +\n>> + uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4];\n>> +} MSF2SysregState;\n>> +\n>> +#endif /* HW_MSF2_SYSREG_H */\n>>\n>>\n> Acked-by: Philippe Mathieu-Daudé \n> Tested-by: Philippe Mathieu-Daudé \n>\n\nThank you,\nSundeep","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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(PDT)","MIME-Version":"1.0","In-Reply-To":"<2c6a4136-fb80-2000-940c-1df5e718cbf1@amsat.org>","References":"<1505494753-10837-1-git-send-email-sundeep.lkml@gmail.com>\n\t<1505494753-10837-3-git-send-email-sundeep.lkml@gmail.com>\n\t<2c6a4136-fb80-2000-940c-1df5e718cbf1@amsat.org>","From":"sundeep subbaraya ","Date":"Mon, 18 Sep 2017 15:47:52 +0530","Message-ID":"","To":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400c:c08::233","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-Content-Filtered-By":"Mailman/MimeDel 2.1.21","Subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell , qemu-arm ,\n\tQEMU Developers ,\n\tAlistair Francis ,\n\tPeter Crosthwaite ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1770066,"web_url":"http://patchwork.ozlabs.org/comment/1770066/","msgid":"","list_archive_url":null,"date":"2017-09-18T10:35:04","subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 18 September 2017 at 11:17, sundeep subbaraya wrote:\n> Hi Philippe,\n>\n> On Mon, Sep 18, 2017 at 6:31 AM, Philippe Mathieu-Daudé \n> wrote:\n>>\n>> Hi Sundeep, Peter,\n>>\n>>\n>> On 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:\n>>>\n>>> Added Sytem register block of Smartfusion2.\n>>> This block has PLL registers which are accessed by guest.\n>>>\n>>> Signed-off-by: Subbaraya Sundeep \n>>> Reviewed-by: Alistair Francis \n>>> ---\n>>> hw/misc/Makefile.objs | 1 +\n>>> hw/misc/msf2-sysreg.c | 168\n>>> ++++++++++++++++++++++++++++++++++++++++++\n>>> hw/misc/trace-events | 5 ++\n>>> include/hw/misc/msf2-sysreg.h | 77 +++++++++++++++++++\n>>> 4 files changed, 251 insertions(+)\n>>> create mode 100644 hw/misc/msf2-sysreg.c\n>>> create mode 100644 include/hw/misc/msf2-sysreg.h\n>>>\n>>> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs\n>>> index 29fb922..e8f0a02 100644\n>>> --- a/hw/misc/Makefile.objs\n>>> +++ b/hw/misc/Makefile.objs\n>>> @@ -59,3 +59,4 @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o\n>>> obj-$(CONFIG_AUX) += auxbus.o\n>>> obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o\n>>> obj-y += mmio_interface.o\n>>> +obj-$(CONFIG_MSF2) += msf2-sysreg.o\n>>> diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c\n>>> new file mode 100644\n>>> index 0000000..dc3597b\n>>> --- /dev/null\n>>> +++ b/hw/misc/msf2-sysreg.c\n>>> @@ -0,0 +1,168 @@\n>>> +/*\n>>> + * System Register block model of Microsemi SmartFusion2.\n>>> + *\n>>> + * Copyright (c) 2017 Subbaraya Sundeep \n>>> + *\n>>> + * This program is free software; you can redistribute it and/or\n>>> + * modify it under the terms of the GNU General Public License\n>>> + * as published by the Free Software Foundation; either version\n>>> + * 2 of the License, or (at your option) any later version.\n>>> + *\n>>> + * You should have received a copy of the GNU General Public License\n>>> along\n>>> + * with this program; if not, see .\n>>> + */\n>>> +\n>>> +#include \"qemu/osdep.h\"\n>>> +#include \"qemu/log.h\"\n>>> +#include \"hw/misc/msf2-sysreg.h\"\n>>> +#include \"trace.h\"\n>>> +\n>>> +static inline int msf2_divbits(uint32_t div)\n>>> +{\n>>> + int ret = 0;\n>>> +\n>>> + switch (div) {\n>>> + case 1:\n>>> + ret = 0;\n>>> + break;\n>>> + case 2:\n>>> + ret = 1;\n>>> + break;\n>>> + case 4:\n>>> + ret = 2;\n>>> + break;\n>>> + case 8:\n>>> + ret = 4;\n>>> + break;\n>>> + case 16:\n>>> + ret = 5;\n>>> + break;\n>>> + case 32:\n>>> + ret = 6;\n>>> + break;\n>>> + default:\n>>> + break;\n>>\n>>\n>> eh?\n>>\n>>> + }\n>>> +\n>>> + return ret;\n>>> +}\n>>> +\n>>> +static void msf2_sysreg_reset(DeviceState *d)\n>>> +{\n>>> + MSF2SysregState *s = MSF2_SYSREG(d);\n>>> +\n>>> + s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;\n>>> + s->regs[MSSDDR_PLL_STATUS] = 0x3;\n>>> + s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |\n>>\n>>\n>> ctz32(s->apb0div) << 5 ...\n>\n>\n> I will modify like below:\n> div0 = s->apb0div < 8 ? ctz32(s->apb0div) : ctz32(s->apb0div) + 1;\n> div1 = s->apb1div < 8 ? ctz32(s->apb1div) : ctz32(s->apb1div) + 1;\n\nI think you should keep an msf2_divbits() function for that,\neven if it's only\n\nstatic inline int msf2_divbits(uint32_t div)\n{\n int r = ctz32(div);\n\n return (div < 8) ? r : r + 1;\n}\n\nthanks\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"JACVHmFn\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwj8Z4C29z9s78\n\tfor ;\n\tMon, 18 Sep 2017 20:35:58 +1000 (AEST)","from localhost ([::1]:35685 helo=lists.gnu.org)\n\tby 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(PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<1505494753-10837-1-git-send-email-sundeep.lkml@gmail.com>\n\t<1505494753-10837-3-git-send-email-sundeep.lkml@gmail.com>\n\t<2c6a4136-fb80-2000-940c-1df5e718cbf1@amsat.org>\n\t","From":"Peter Maydell ","Date":"Mon, 18 Sep 2017 11:35:04 +0100","Message-ID":"","To":"sundeep subbaraya ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c0c::22d","Subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Francis , Peter Crosthwaite\n\t, \tqemu-arm ,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ,\n\tQEMU Developers ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1770157,"web_url":"http://patchwork.ozlabs.org/comment/1770157/","msgid":"","list_archive_url":null,"date":"2017-09-18T13:25:23","subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","submitter":{"id":64324,"url":"http://patchwork.ozlabs.org/api/people/64324/","name":"sundeep subbaraya","email":"sundeep.lkml@gmail.com"},"content":"H Peter,\n\nOn Mon, Sep 18, 2017 at 4:05 PM, Peter Maydell \nwrote:\n\n> On 18 September 2017 at 11:17, sundeep subbaraya \n> wrote:\n> > Hi Philippe,\n> >\n> > On Mon, Sep 18, 2017 at 6:31 AM, Philippe Mathieu-Daudé >\n> > wrote:\n> >>\n> >> Hi Sundeep, Peter,\n> >>\n> >>\n> >> On 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:\n> >>>\n> >>> Added Sytem register block of Smartfusion2.\n> >>> This block has PLL registers which are accessed by guest.\n> >>>\n> >>> Signed-off-by: Subbaraya Sundeep \n> >>> Reviewed-by: Alistair Francis \n> >>> ---\n> >>> hw/misc/Makefile.objs | 1 +\n> >>> hw/misc/msf2-sysreg.c | 168\n> >>> ++++++++++++++++++++++++++++++++++++++++++\n> >>> hw/misc/trace-events | 5 ++\n> >>> include/hw/misc/msf2-sysreg.h | 77 +++++++++++++++++++\n> >>> 4 files changed, 251 insertions(+)\n> >>> create mode 100644 hw/misc/msf2-sysreg.c\n> >>> create mode 100644 include/hw/misc/msf2-sysreg.h\n> >>>\n> >>> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs\n> >>> index 29fb922..e8f0a02 100644\n> >>> --- a/hw/misc/Makefile.objs\n> >>> +++ b/hw/misc/Makefile.objs\n> >>> @@ -59,3 +59,4 @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o\n> >>> obj-$(CONFIG_AUX) += auxbus.o\n> >>> obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o\n> >>> obj-y += mmio_interface.o\n> >>> +obj-$(CONFIG_MSF2) += msf2-sysreg.o\n> >>> diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c\n> >>> new file mode 100644\n> >>> index 0000000..dc3597b\n> >>> --- /dev/null\n> >>> +++ b/hw/misc/msf2-sysreg.c\n> >>> @@ -0,0 +1,168 @@\n> >>> +/*\n> >>> + * System Register block model of Microsemi SmartFusion2.\n> >>> + *\n> >>> + * Copyright (c) 2017 Subbaraya Sundeep \n> >>> + *\n> >>> + * This program is free software; you can redistribute it and/or\n> >>> + * modify it under the terms of the GNU General Public License\n> >>> + * as published by the Free Software Foundation; either version\n> >>> + * 2 of the License, or (at your option) any later version.\n> >>> + *\n> >>> + * You should have received a copy of the GNU General Public License\n> >>> along\n> >>> + * with this program; if not, see .\n> >>> + */\n> >>> +\n> >>> +#include \"qemu/osdep.h\"\n> >>> +#include \"qemu/log.h\"\n> >>> +#include \"hw/misc/msf2-sysreg.h\"\n> >>> +#include \"trace.h\"\n> >>> +\n> >>> +static inline int msf2_divbits(uint32_t div)\n> >>> +{\n> >>> + int ret = 0;\n> >>> +\n> >>> + switch (div) {\n> >>> + case 1:\n> >>> + ret = 0;\n> >>> + break;\n> >>> + case 2:\n> >>> + ret = 1;\n> >>> + break;\n> >>> + case 4:\n> >>> + ret = 2;\n> >>> + break;\n> >>> + case 8:\n> >>> + ret = 4;\n> >>> + break;\n> >>> + case 16:\n> >>> + ret = 5;\n> >>> + break;\n> >>> + case 32:\n> >>> + ret = 6;\n> >>> + break;\n> >>> + default:\n> >>> + break;\n> >>\n> >>\n> >> eh?\n> >>\n> >>> + }\n> >>> +\n> >>> + return ret;\n> >>> +}\n> >>> +\n> >>> +static void msf2_sysreg_reset(DeviceState *d)\n> >>> +{\n> >>> + MSF2SysregState *s = MSF2_SYSREG(d);\n> >>> +\n> >>> + s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;\n> >>> + s->regs[MSSDDR_PLL_STATUS] = 0x3;\n> >>> + s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |\n> >>\n> >>\n> >> ctz32(s->apb0div) << 5 ...\n> >\n> >\n> > I will modify like below:\n> > div0 = s->apb0div < 8 ? ctz32(s->apb0div) : ctz32(s->apb0div) + 1;\n> > div1 = s->apb1div < 8 ? ctz32(s->apb1div) : ctz32(s->apb1div) + 1;\n>\n> I think you should keep an msf2_divbits() function for that,\n> even if it's only\n>\n> static inline int msf2_divbits(uint32_t div)\n> {\n> int r = ctz32(div);\n>\n> return (div < 8) ? r : r + 1;\n> }\n>\n> Ok will change like this.\n\nThanks,\nSundeep\n\n\n> thanks\n> -- PMM\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"n5a0vyrp\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwmwk5Xxcz9s3w\n\tfor ;\n\tMon, 18 Sep 2017 23:25:58 +1000 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(PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<1505494753-10837-1-git-send-email-sundeep.lkml@gmail.com>\n\t<1505494753-10837-3-git-send-email-sundeep.lkml@gmail.com>\n\t<2c6a4136-fb80-2000-940c-1df5e718cbf1@amsat.org>\n\t\n\t","From":"sundeep subbaraya ","Date":"Mon, 18 Sep 2017 18:55:23 +0530","Message-ID":"","To":"Peter Maydell ","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400c:c05::243","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-Content-Filtered-By":"Mailman/MimeDel 2.1.21","Subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Francis , Peter Crosthwaite\n\t, \tqemu-arm ,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ,\n\tQEMU Developers ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1770159,"web_url":"http://patchwork.ozlabs.org/comment/1770159/","msgid":"","list_archive_url":null,"date":"2017-09-18T13:27:02","subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","submitter":{"id":64324,"url":"http://patchwork.ozlabs.org/api/people/64324/","name":"sundeep subbaraya","email":"sundeep.lkml@gmail.com"},"content":"Hi Peter,\n\nOn Mon, Sep 18, 2017 at 3:47 PM, sundeep subbaraya \nwrote:\n\n> Hi Philippe,\n>\n> On Mon, Sep 18, 2017 at 6:31 AM, Philippe Mathieu-Daudé \n> wrote:\n>\n>> Hi Sundeep, Peter,\n>>\n>>\n>> On 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:\n>>\n>>> Added Sytem register block of Smartfusion2.\n>>> This block has PLL registers which are accessed by guest.\n>>>\n>>> Signed-off-by: Subbaraya Sundeep \n>>> Reviewed-by: Alistair Francis \n>>> ---\n>>> hw/misc/Makefile.objs | 1 +\n>>> hw/misc/msf2-sysreg.c | 168 ++++++++++++++++++++++++++++++\n>>> ++++++++++++\n>>> hw/misc/trace-events | 5 ++\n>>> include/hw/misc/msf2-sysreg.h | 77 +++++++++++++++++++\n>>> 4 files changed, 251 insertions(+)\n>>> create mode 100644 hw/misc/msf2-sysreg.c\n>>> create mode 100644 include/hw/misc/msf2-sysreg.h\n>>>\n>>> diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs\n>>> index 29fb922..e8f0a02 100644\n>>> --- a/hw/misc/Makefile.objs\n>>> +++ b/hw/misc/Makefile.objs\n>>> @@ -59,3 +59,4 @@ obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o\n>>> obj-$(CONFIG_AUX) += auxbus.o\n>>> obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o\n>>> obj-y += mmio_interface.o\n>>> +obj-$(CONFIG_MSF2) += msf2-sysreg.o\n>>> diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c\n>>> new file mode 100644\n>>> index 0000000..dc3597b\n>>> --- /dev/null\n>>> +++ b/hw/misc/msf2-sysreg.c\n>>> @@ -0,0 +1,168 @@\n>>> +/*\n>>> + * System Register block model of Microsemi SmartFusion2.\n>>> + *\n>>> + * Copyright (c) 2017 Subbaraya Sundeep \n>>> + *\n>>> + * This program is free software; you can redistribute it and/or\n>>> + * modify it under the terms of the GNU General Public License\n>>> + * as published by the Free Software Foundation; either version\n>>> + * 2 of the License, or (at your option) any later version.\n>>> + *\n>>> + * You should have received a copy of the GNU General Public License\n>>> along\n>>> + * with this program; if not, see .\n>>> + */\n>>> +\n>>> +#include \"qemu/osdep.h\"\n>>> +#include \"qemu/log.h\"\n>>> +#include \"hw/misc/msf2-sysreg.h\"\n>>> +#include \"trace.h\"\n>>> +\n>>> +static inline int msf2_divbits(uint32_t div)\n>>> +{\n>>> + int ret = 0;\n>>> +\n>>> + switch (div) {\n>>> + case 1:\n>>> + ret = 0;\n>>> + break;\n>>> + case 2:\n>>> + ret = 1;\n>>> + break;\n>>> + case 4:\n>>> + ret = 2;\n>>> + break;\n>>> + case 8:\n>>> + ret = 4;\n>>> + break;\n>>> + case 16:\n>>> + ret = 5;\n>>> + break;\n>>> + case 32:\n>>> + ret = 6;\n>>> + break;\n>>> + default:\n>>> + break;\n>>>\n>>\n>> eh?\n>>\n>> + }\n>>> +\n>>> + return ret;\n>>> +}\n>>> +\n>>> +static void msf2_sysreg_reset(DeviceState *d)\n>>> +{\n>>> + MSF2SysregState *s = MSF2_SYSREG(d);\n>>> +\n>>> + s->regs[MSSDDR_PLL_STATUS_LOW_CR] = 0x021A2358;\n>>> + s->regs[MSSDDR_PLL_STATUS] = 0x3;\n>>> + s->regs[MSSDDR_FACC1_CR] = msf2_divbits(s->apb0div) << 5 |\n>>>\n>>\n>> ctz32(s->apb0div) << 5 ...\n>\n>\n> I will modify like below:\n> div0 = s->apb0div < 8 ? ctz32(s->apb0div) : ctz32(s->apb0div) + 1;\n> div1 = s->apb1div < 8 ? ctz32(s->apb1div) : ctz32(s->apb1div) + 1;\n> s->regs[MSSDDR_FACC1_CR] = div0 << 5 | div1 << 2;\n>\n>\n>>\n>> + msf2_divbits(s->apb1div) << 2;\n>>> +}\n>>> +\n>>> +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset,\n>>> + unsigned size)\n>>> +{\n>>> + MSF2SysregState *s = opaque;\n>>> + uint32_t ret = 0;\n>>> +\n>>> + offset >>= 2;\n>>> + if (offset < ARRAY_SIZE(s->regs)) {\n>>> + ret = s->regs[offset];\n>>> + trace_msf2_sysreg_read(offset << 2, ret);\n>>> + } else {\n>>> + qemu_log_mask(LOG_GUEST_ERROR,\n>>> + \"%s: Bad offset 0x%08\" HWADDR_PRIx \"\\n\", __func__,\n>>> + offset << 2);\n>>> + }\n>>> +\n>>> + return ret;\n>>> +}\n>>> +\n>>> +static void msf2_sysreg_write(void *opaque, hwaddr offset,\n>>> + uint64_t val, unsigned size)\n>>> +{\n>>> + MSF2SysregState *s = opaque;\n>>> + uint32_t newval = val;\n>>> +\n>>> + offset >>= 2;\n>>> +\n>>> + switch (offset) {\n>>> + case MSSDDR_PLL_STATUS:\n>>> + trace_msf2_sysreg_write_pll_status();\n>>> + break;\n>>> +\n>>> + case ESRAM_CR:\n>>> + case DDR_CR:\n>>> + case ENVM_REMAP_BASE_CR:\n>>> + if (newval != s->regs[offset]) {\n>>> + qemu_log_mask(LOG_UNIMP,\n>>> + TYPE_MSF2_SYSREG\": remapping not supported\\n\");\n>>>\n>>\n>> I'd rather exit here than continue with inconsistent cpu, Peter what do\n>> you recommend?\n>\n>\nCould you please suggest.\n\nThanks,\nSundeep\n\n>\n>>\n>> + }\n>>> + break;\n>>> +\n>>> + default:\n>>> + if (offset < ARRAY_SIZE(s->regs)) {\n>>> + trace_msf2_sysreg_write(offset << 2, newval,\n>>> s->regs[offset]);\n>>> + s->regs[offset] = newval;\n>>> + } else {\n>>> + qemu_log_mask(LOG_GUEST_ERROR,\n>>> + \"%s: Bad offset 0x%08\" HWADDR_PRIx \"\\n\",\n>>> __func__,\n>>> + offset << 2);\n>>> + }\n>>> + break;\n>>> + }\n>>> +}\n>>> +\n>>> +static const MemoryRegionOps sysreg_ops = {\n>>> + .read = msf2_sysreg_read,\n>>> + .write = msf2_sysreg_write,\n>>> + .endianness = DEVICE_NATIVE_ENDIAN,\n>>> +};\n>>> +\n>>> +static void msf2_sysreg_init(Object *obj)\n>>> +{\n>>> + MSF2SysregState *s = MSF2_SYSREG(obj);\n>>> +\n>>> + memory_region_init_io(&s->iomem, obj, &sysreg_ops, s,\n>>> TYPE_MSF2_SYSREG,\n>>> + MSF2_SYSREG_MMIO_SIZE);\n>>> + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);\n>>> +}\n>>> +\n>>> +static const VMStateDescription vmstate_msf2_sysreg = {\n>>> + .name = TYPE_MSF2_SYSREG,\n>>> + .version_id = 1,\n>>> + .minimum_version_id = 1,\n>>> + .fields = (VMStateField[]) {\n>>> + VMSTATE_UINT32_ARRAY(regs, MSF2SysregState,\n>>> MSF2_SYSREG_MMIO_SIZE / 4),\n>>> + VMSTATE_END_OF_LIST()\n>>> + }\n>>> +};\n>>> +\n>>> +static Property msf2_sysreg_properties[] = {\n>>> + /* default divisors in Libero GUI */\n>>> + DEFINE_PROP_UINT32(\"apb0divisor\", MSF2SysregState, apb0div, 2),\n>>> + DEFINE_PROP_UINT32(\"apb1divisor\", MSF2SysregState, apb1div, 2),\n>>>\n>>\n>> DEFINE_PROP_UINT8() is enough for both.\n>>\n>> Beware these divisors must be power of 2, and maximum 32.\n>\n> This can be checked in msf2_sysreg_realize() ...\n>\n>\n> Ok\n>\n>>\n>>\n>> + DEFINE_PROP_END_OF_LIST(),\n>>> +};\n>>> +\n>>> +static void msf2_sysreg_class_init(ObjectClass *klass, void *data)\n>>> +{\n>>> + DeviceClass *dc = DEVICE_CLASS(klass);\n>>> +\n>>> + dc->vmsd = &vmstate_msf2_sysreg;\n>>> + dc->reset = msf2_sysreg_reset;\n>>>\n>>\n>> ... which would go here:\n>>\n>> dc->realize = msf2_sysreg_realize;\n>>\n>> Ok.\n>\n>>\n>> + dc->props = msf2_sysreg_properties;\n>>> +}\n>>> +\n>>> +static const TypeInfo msf2_sysreg_info = {\n>>> + .name = TYPE_MSF2_SYSREG,\n>>> + .parent = TYPE_SYS_BUS_DEVICE,\n>>> + .class_init = msf2_sysreg_class_init,\n>>> + .instance_size = sizeof(MSF2SysregState),\n>>> + .instance_init = msf2_sysreg_init,\n>>> +};\n>>> +\n>>> +static void msf2_sysreg_register_types(void)\n>>> +{\n>>> + type_register_static(&msf2_sysreg_info);\n>>> +}\n>>> +\n>>> +type_init(msf2_sysreg_register_types)\n>>> diff --git a/hw/misc/trace-events b/hw/misc/trace-events\n>>> index 3313585..616579a 100644\n>>> --- a/hw/misc/trace-events\n>>> +++ b/hw/misc/trace-events\n>>> @@ -61,3 +61,8 @@ mps2_scc_reset(void) \"MPS2 SCC: reset\"\n>>> mps2_scc_leds(char led7, char led6, char led5, char led4, char led3,\n>>> char led2, char led1, char led0) \"MPS2 SCC LEDs: %c%c%c%c%c%c%c%c\"\n>>> mps2_scc_cfg_write(unsigned function, unsigned device, uint32_t value)\n>>> \"MPS2 SCC config write: function %d device %d data 0x%\" PRIx32\n>>> mps2_scc_cfg_read(unsigned function, unsigned device, uint32_t value)\n>>> \"MPS2 SCC config read: function %d device %d data 0x%\" PRIx32\n>>> +\n>>> +# hw/misc/msf2-sysreg.c\n>>> +msf2_sysreg_write(uint64_t offset, uint32_t val, uint32_t prev)\n>>> \"msf2-sysreg write: addr 0x%08\" HWADDR_PRIx \" data 0x%\" PRIx32 \" prev 0x%\"\n>>> PRIx32\n>>> +msf2_sysreg_read(uint64_t offset, uint32_t val) \"msf2-sysreg read: addr\n>>> 0x%08\" HWADDR_PRIx \" data 0x%08\" PRIx32\n>>> +msf2_sysreg_write_pll_status(void) \"Invalid write to read only PLL\n>>> status register\"\n>>> diff --git a/include/hw/misc/msf2-sysreg.h\n>>> b/include/hw/misc/msf2-sysreg.h\n>>> new file mode 100644\n>>> index 0000000..231f827\n>>> --- /dev/null\n>>> +++ b/include/hw/misc/msf2-sysreg.h\n>>> @@ -0,0 +1,77 @@\n>>> +/*\n>>> + * Microsemi SmartFusion2 SYSREG\n>>> + *\n>>> + * Copyright (c) 2017 Subbaraya Sundeep \n>>> + *\n>>> + * Permission is hereby granted, free of charge, to any person\n>>> obtaining a copy\n>>> + * of this software and associated documentation files (the\n>>> \"Software\"), to deal\n>>> + * in the Software without restriction, including without limitation\n>>> the rights\n>>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or\n>>> sell\n>>> + * copies of the Software, and to permit persons to whom the Software is\n>>> + * furnished to do so, subject to the following conditions:\n>>> + *\n>>> + * The above copyright notice and this permission notice shall be\n>>> included in\n>>> + * all copies or substantial portions of the Software.\n>>> + *\n>>> + * THE SOFTWARE IS PROVIDED \"AS IS\", WITHOUT WARRANTY OF ANY KIND,\n>>> EXPRESS OR\n>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\n>>> MERCHANTABILITY,\n>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT\n>>> SHALL\n>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR\n>>> OTHER\n>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,\n>>> ARISING FROM,\n>>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER\n>>> DEALINGS IN\n>>> + * THE SOFTWARE.\n>>> + */\n>>> +\n>>> +#ifndef HW_MSF2_SYSREG_H\n>>> +#define HW_MSF2_SYSREG_H\n>>> +\n>>> +#include \"hw/sysbus.h\"\n>>> +\n>>> +enum {\n>>> + ESRAM_CR = 0x00 / 4,\n>>> + ESRAM_MAX_LAT,\n>>> + DDR_CR,\n>>> + ENVM_CR,\n>>> + ENVM_REMAP_BASE_CR,\n>>> + ENVM_REMAP_FAB_CR,\n>>> + CC_CR,\n>>> + CC_REGION_CR,\n>>> + CC_LOCK_BASE_ADDR_CR,\n>>> + CC_FLUSH_INDX_CR,\n>>> + DDRB_BUF_TIMER_CR,\n>>> + DDRB_NB_ADDR_CR,\n>>> + DDRB_NB_SIZE_CR,\n>>> + DDRB_CR,\n>>> +\n>>> + SOFT_RESET_CR = 0x48 / 4,\n>>> + M3_CR,\n>>> +\n>>> + GPIO_SYSRESET_SEL_CR = 0x58 / 4,\n>>> +\n>>> + MDDR_CR = 0x60 / 4,\n>>> +\n>>> + MSSDDR_PLL_STATUS_LOW_CR = 0x90 / 4,\n>>> + MSSDDR_PLL_STATUS_HIGH_CR,\n>>> + MSSDDR_FACC1_CR,\n>>> + MSSDDR_FACC2_CR,\n>>> +\n>>> + MSSDDR_PLL_STATUS = 0x150 / 4,\n>>> +};\n>>> +\n>>> +#define MSF2_SYSREG_MMIO_SIZE 0x300\n>>> +\n>>> +#define TYPE_MSF2_SYSREG \"msf2-sysreg\"\n>>> +#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj),\n>>> TYPE_MSF2_SYSREG)\n>>> +\n>>> +typedef struct MSF2SysregState {\n>>> + SysBusDevice parent_obj;\n>>> +\n>>> + MemoryRegion iomem;\n>>> +\n>>> + uint32_t apb0div;\n>>> + uint32_t apb1div;\n>>>\n>>\n>> uint8_t for both\n>\n>\n> Ok.\n>\n>>\n>>\n>> +\n>>> + uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4];\n>>> +} MSF2SysregState;\n>>> +\n>>> +#endif /* HW_MSF2_SYSREG_H */\n>>>\n>>>\n>> Acked-by: Philippe Mathieu-Daudé \n>> Tested-by: Philippe Mathieu-Daudé \n>>\n>\n> Thank you,\n> Sundeep\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-Content-Filtered-By":"Mailman/MimeDel 2.1.21","Subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell , qemu-arm ,\n\tQEMU Developers ,\n\tAlistair Francis ,\n\tPeter Crosthwaite ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1770164,"web_url":"http://patchwork.ozlabs.org/comment/1770164/","msgid":"","list_archive_url":null,"date":"2017-09-18T13:36:23","subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 18 September 2017 at 14:27, sundeep subbaraya wrote:\n> Hi Peter,\n>\n> On Mon, Sep 18, 2017 at 3:47 PM, sundeep subbaraya \n> wrote:\n>>\n>> Hi Philippe,\n>>\n>> On Mon, Sep 18, 2017 at 6:31 AM, Philippe Mathieu-Daudé \n>> wrote:\n>>>\n>>> Hi Sundeep, Peter,\n>>>\n>>>\n>>> On 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:\n>>>>\n>>>> +static void msf2_sysreg_write(void *opaque, hwaddr offset,\n>>>> + uint64_t val, unsigned size)\n>>>> +{\n>>>> + MSF2SysregState *s = opaque;\n>>>> + uint32_t newval = val;\n>>>> +\n>>>> + offset >>= 2;\n>>>> +\n>>>> + switch (offset) {\n>>>> + case MSSDDR_PLL_STATUS:\n>>>> + trace_msf2_sysreg_write_pll_status();\n>>>> + break;\n>>>> +\n>>>> + case ESRAM_CR:\n>>>> + case DDR_CR:\n>>>> + case ENVM_REMAP_BASE_CR:\n>>>> + if (newval != s->regs[offset]) {\n>>>> + qemu_log_mask(LOG_UNIMP,\n>>>> + TYPE_MSF2_SYSREG\": remapping not supported\\n\");\n>>>\n>>>\n>>> I'd rather exit here than continue with inconsistent cpu, Peter what do\n>>> you recommend?\n>\n>\n> Could you please suggest.\n\nWe shouldn't exit QEMU for something the guest can provoke. If\nthe functionality isn't implemented then just LOG_UNIMP it.\n\nthanks\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"kukxe3bk\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwn9m1z16z9s4s\n\tfor ;\n\tMon, 18 Sep 2017 23:37:12 +1000 (AEST)","from localhost ([::1]:36692 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dtwEY-00012B-3L\n\tfor incoming@patchwork.ozlabs.org; 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charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::22f","Subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Francis , Peter Crosthwaite\n\t, \tqemu-arm ,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ,\n\tQEMU Developers ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1770184,"web_url":"http://patchwork.ozlabs.org/comment/1770184/","msgid":"<6947945c-6b04-dce0-9010-b3350df0f151@amsat.org>","list_archive_url":null,"date":"2017-09-18T13:58:06","subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"Hi Peter,\n\nOn 09/18/2017 10:36 AM, Peter Maydell wrote:\n> On 18 September 2017 at 14:27, sundeep subbaraya wrote:\n>>>> Hi Sundeep, Peter,\n>>>>\n>>>>\n>>>> On 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:\n>>>>>\n>>>>> +static void msf2_sysreg_write(void *opaque, hwaddr offset,\n>>>>> + uint64_t val, unsigned size)\n>>>>> +{\n>>>>> + MSF2SysregState *s = opaque;\n>>>>> + uint32_t newval = val;\n>>>>> +\n>>>>> + offset >>= 2;\n>>>>> +\n>>>>> + switch (offset) {\n>>>>> + case MSSDDR_PLL_STATUS:\n>>>>> + trace_msf2_sysreg_write_pll_status();\n>>>>> + break;\n>>>>> +\n>>>>> + case ESRAM_CR:\n>>>>> + case DDR_CR:\n>>>>> + case ENVM_REMAP_BASE_CR:\n>>>>> + if (newval != s->regs[offset]) {\n>>>>> + qemu_log_mask(LOG_UNIMP,\n>>>>> + TYPE_MSF2_SYSREG\": remapping not supported\\n\");\n>>>>\n>>>>\n>>>> I'd rather exit here than continue with inconsistent cpu, Peter what do\n>>>> you recommend?\n>>\n>>\n>> Could you please suggest.\n> \n> We shouldn't exit QEMU for something the guest can provoke. If\n> the functionality isn't implemented then just LOG_UNIMP it.\n\nThis was commented here:\nhttp://lists.nongnu.org/archive/html/qemu-devel/2017-05/msg02971.html\n\nGuest remapping code is like non-return function. Hardware error here \ncan not happen, so there is no more guest code after a remap request.\nContinuing running QEMU will lead to chaos, that's why I recommend \naborting instead of just LOG_UNIMP it.\n\nRegards,\n\nPhil.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"t4paXiop\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwng12ZFqz9s7M\n\tfor ;\n\tMon, 18 Sep 2017 23:59:09 +1000 (AEST)","from localhost ([::1]:36772 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dtwZn-0000rf-Fh\n\tfor incoming@patchwork.ozlabs.org; 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\n\tMon, 18 Sep 2017 06:58:10 -0700 (PDT)","To":"Peter Maydell ,\n\tsundeep subbaraya ","References":"<1505494753-10837-1-git-send-email-sundeep.lkml@gmail.com>\n\t<1505494753-10837-3-git-send-email-sundeep.lkml@gmail.com>\n\t<2c6a4136-fb80-2000-940c-1df5e718cbf1@amsat.org>\n\t\n\t\n\t","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Message-ID":"<6947945c-6b04-dce0-9010-b3350df0f151@amsat.org>","Date":"Mon, 18 Sep 2017 10:58:06 -0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::243","Subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Francis , qemu-arm , \n\tQEMU Developers ,\n\tPeter Crosthwaite ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1770188,"web_url":"http://patchwork.ozlabs.org/comment/1770188/","msgid":"","list_archive_url":null,"date":"2017-09-18T14:00:42","subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 18 September 2017 at 14:58, Philippe Mathieu-Daudé wrote:\n> Hi Peter,\n>\n> On 09/18/2017 10:36 AM, Peter Maydell wrote:\n>>\n>> On 18 September 2017 at 14:27, sundeep subbaraya \n>> wrote:\n>>>>>\n>>>>> Hi Sundeep, Peter,\n>>>>>\n>>>>>\n>>>>> On 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:\n>>>>>>\n>>>>>>\n>>>>>> +static void msf2_sysreg_write(void *opaque, hwaddr offset,\n>>>>>> + uint64_t val, unsigned size)\n>>>>>> +{\n>>>>>> + MSF2SysregState *s = opaque;\n>>>>>> + uint32_t newval = val;\n>>>>>> +\n>>>>>> + offset >>= 2;\n>>>>>> +\n>>>>>> + switch (offset) {\n>>>>>> + case MSSDDR_PLL_STATUS:\n>>>>>> + trace_msf2_sysreg_write_pll_status();\n>>>>>> + break;\n>>>>>> +\n>>>>>> + case ESRAM_CR:\n>>>>>> + case DDR_CR:\n>>>>>> + case ENVM_REMAP_BASE_CR:\n>>>>>> + if (newval != s->regs[offset]) {\n>>>>>> + qemu_log_mask(LOG_UNIMP,\n>>>>>> + TYPE_MSF2_SYSREG\": remapping not\n>>>>>> supported\\n\");\n>>>>>\n>>>>>\n>>>>>\n>>>>> I'd rather exit here than continue with inconsistent cpu, Peter what do\n>>>>> you recommend?\n>>>\n>>>\n>>>\n>>> Could you please suggest.\n>>\n>>\n>> We shouldn't exit QEMU for something the guest can provoke. If\n>> the functionality isn't implemented then just LOG_UNIMP it.\n>\n>\n> This was commented here:\n> http://lists.nongnu.org/archive/html/qemu-devel/2017-05/msg02971.html\n>\n> Guest remapping code is like non-return function. Hardware error here can\n> not happen, so there is no more guest code after a remap request.\n> Continuing running QEMU will lead to chaos, that's why I recommend aborting\n> instead of just LOG_UNIMP it.\n\nThere's lots of stuff that can cause the guest to go badly\nand confusingly wrong if unimplemented. If we print a\nuseful message with LOG_UNIMP then there's an easy clue\nfor what's gone wrong. The guest shouldn't be able to\nprovoke QEMU to exit.\n\nthanks\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"Fw+Zo0ec\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwntb0V43z9s7G\n\tfor ;\n\tTue, 19 Sep 2017 00:09:09 +1000 (AEST)","from localhost ([::1]:36839 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dtwjT-0000tx-7e\n\tfor incoming@patchwork.ozlabs.org; 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charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::22f","Subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Francis ,\n\tPeter Crosthwaite ,\n\tqemu-arm , QEMU Developers , \n\tsundeep subbaraya ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1770198,"web_url":"http://patchwork.ozlabs.org/comment/1770198/","msgid":"<1abcfaca-3af0-efcf-d577-c3c5cb39e8fe@amsat.org>","list_archive_url":null,"date":"2017-09-18T14:22:28","subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"content":"On 09/18/2017 11:00 AM, Peter Maydell wrote:\n> On 18 September 2017 at 14:58, Philippe Mathieu-Daudé wrote:\n>> Hi Peter,\n>>\n>> On 09/18/2017 10:36 AM, Peter Maydell wrote:\n>>>\n>>> On 18 September 2017 at 14:27, sundeep subbaraya \n>>> wrote:\n>>>>>>\n>>>>>> Hi Sundeep, Peter,\n>>>>>>\n>>>>>>\n>>>>>> On 09/15/2017 01:59 PM, Subbaraya Sundeep wrote:\n>>>>>>>\n>>>>>>>\n>>>>>>> +static void msf2_sysreg_write(void *opaque, hwaddr offset,\n>>>>>>> + uint64_t val, unsigned size)\n>>>>>>> +{\n>>>>>>> + MSF2SysregState *s = opaque;\n>>>>>>> + uint32_t newval = val;\n>>>>>>> +\n>>>>>>> + offset >>= 2;\n>>>>>>> +\n>>>>>>> + switch (offset) {\n>>>>>>> + case MSSDDR_PLL_STATUS:\n>>>>>>> + trace_msf2_sysreg_write_pll_status();\n>>>>>>> + break;\n>>>>>>> +\n>>>>>>> + case ESRAM_CR:\n>>>>>>> + case DDR_CR:\n>>>>>>> + case ENVM_REMAP_BASE_CR:\n>>>>>>> + if (newval != s->regs[offset]) {\n>>>>>>> + qemu_log_mask(LOG_UNIMP,\n>>>>>>> + TYPE_MSF2_SYSREG\": remapping not\n>>>>>>> supported\\n\");\n>>>>>>\n>>>>>>\n>>>>>>\n>>>>>> I'd rather exit here than continue with inconsistent cpu, Peter what do\n>>>>>> you recommend?\n>>>>\n>>>>\n>>>>\n>>>> Could you please suggest.\n>>>\n>>>\n>>> We shouldn't exit QEMU for something the guest can provoke. If\n>>> the functionality isn't implemented then just LOG_UNIMP it.\n>>\n>>\n>> This was commented here:\n>> http://lists.nongnu.org/archive/html/qemu-devel/2017-05/msg02971.html\n>>\n>> Guest remapping code is like non-return function. Hardware error here can\n>> not happen, so there is no more guest code after a remap request.\n>> Continuing running QEMU will lead to chaos, that's why I recommend aborting\n>> instead of just LOG_UNIMP it.\n> \n> There's lots of stuff that can cause the guest to go badly\n> and confusingly wrong if unimplemented. If we print a\n> useful message with LOG_UNIMP then there's an easy clue\n> for what's gone wrong. The guest shouldn't be able to\n> provoke QEMU to exit.\n\nI understand. I'm worried about being PITA for an user to figure out \nwhat's happening here, that's why I'm wondering how this should be \nhandled. Another idea I thought about was raising a PREFETCH or BKPT \nexception, but this would also be an incorrect model behavior.\n\nAnyway I'd be happy enough if instead of using LOG_UNIMP/LOG_GUEST_ERROR \nwe use an unconditional qemu_log(\"bus remap unimplemented, unpredictable \nbehaviour!\") warning. Fair enough?\n\nRegards,\n\nPhil.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"ouPYm9pb\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwpDR3lrbz9s7F\n\tfor ;\n\tTue, 19 Sep 2017 00:24:38 +1000 (AEST)","from localhost ([::1]:36960 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dtwyS-0005m3-9c\n\tfor incoming@patchwork.ozlabs.org; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c0d::231","Subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Francis ,\n\tPeter Crosthwaite ,\n\tqemu-arm , QEMU Developers , \n\tsundeep subbaraya ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1770210,"web_url":"http://patchwork.ozlabs.org/comment/1770210/","msgid":"","list_archive_url":null,"date":"2017-09-18T14:39:00","subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 18 September 2017 at 15:22, Philippe Mathieu-Daudé wrote:\n> On 09/18/2017 11:00 AM, Peter Maydell wrote:\n>> There's lots of stuff that can cause the guest to go badly\n>> and confusingly wrong if unimplemented. If we print a\n>> useful message with LOG_UNIMP then there's an easy clue\n>> for what's gone wrong. The guest shouldn't be able to\n>> provoke QEMU to exit.\n>\n>\n> I understand. I'm worried about being PITA for an user to figure out what's\n> happening here, that's why I'm wondering how this should be handled. Another\n> idea I thought about was raising a PREFETCH or BKPT exception, but this\n> would also be an incorrect model behavior.\n>\n> Anyway I'd be happy enough if instead of using LOG_UNIMP/LOG_GUEST_ERROR we\n> use an unconditional qemu_log(\"bus remap unimplemented, unpredictable\n> behaviour!\") warning. Fair enough?\n\nI don't see any reason to handle this any differently to\nanything else.\n\nthanks\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"Xc6t77Ov\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xwpdF49mtz9s7M\n\tfor ;\n\tTue, 19 Sep 2017 00:42:41 +1000 (AEST)","from localhost ([::1]:37043 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dtxFv-0007pv-Ic\n\tfor incoming@patchwork.ozlabs.org; Mon, 18 Sep 2017 10:42:39 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:55793)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dtxCl-0005ao-Q4\n\tfor qemu-devel@nongnu.org; Mon, 18 Sep 2017 10:39:27 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dtxCk-0005ez-V8\n\tfor qemu-devel@nongnu.org; Mon, 18 Sep 2017 10:39:23 -0400","from mail-wm0-x231.google.com ([2a00:1450:400c:c09::231]:47677)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1dtxCk-0005eN-MD\n\tfor qemu-devel@nongnu.org; Mon, 18 Sep 2017 10:39:22 -0400","by mail-wm0-x231.google.com with SMTP id 13so3349238wmq.2\n\tfor ; Mon, 18 Sep 2017 07:39:22 -0700 (PDT)","by 10.223.139.215 with HTTP; Mon, 18 Sep 2017 07:39:00 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc:content-transfer-encoding;\n\tbh=IPkiTVmRXN1dU/SpKJ770xu94nKYt79TikqgdNHSevk=;\n\tb=Xc6t77Ov673sqvuyYjq4+4ixhj5bo5jIftPad+oYNHslavym41svswmrK+l7G58or9\n\tEZQfJtZcLj20NnBVvDhskATxteXatlCL3cIfWOLPzflcSFAAoxugu9NrIslF0gUQ0zvr\n\tT2G8zLnYV/2kD2n+rkaUGuhuyPtuXby/NFny0=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc:content-transfer-encoding;\n\tbh=IPkiTVmRXN1dU/SpKJ770xu94nKYt79TikqgdNHSevk=;\n\tb=gK+jzPZ9H7+iY7bOla5siEZuiIA76sgKeEls7cm7sBXNvqN11y8AoZqbMbP1nHoAXt\n\tC/4uoxDE8h2oSAUIcyDKsdWnr7JyYxqqIHKQU0HD15sE5seQVr9qMqDDURfC6/0QccSW\n\tQEGqUfuCosCXw6LI4yNB+A+FPk4llJm6dHtT4lFeyHLOeDMO1fRxdt5bthQ35P8FzrjF\n\tGT9GzheoQEmmhQGRVthid+LW5mvu6dqYI5kDJxpnpSbxhtcUh7iBctVRbfA06BLV+TBl\n\tkrZQ11m773WGa+0C6aQYkxdlCL0W0a0khz3TuZ10gjGokO0CdDicbX6k+zi+9vLqwW48\n\tSHdg==","X-Gm-Message-State":"AHPjjUjGSAJekvlkvXWNUwz5lYf/iuNkDYuYSMc0sjO8YKletzLmb9Y3\n\tdLZ2tDquRiQFqRMYkD8ImPp3NZ/G5LONYPdyV5OuK/kV","X-Google-Smtp-Source":"AOwi7QDSesMYKwDQOIUVKPN77Zz4IixajFF5nB3j47qg/IRAMgnLIiZUnLdtsB5d6fJPwjWurW4R8ZOBpHgO96CBsks=","X-Received":"by 10.28.52.81 with SMTP id b78mr9140984wma.11.1505745561570;\n\tMon, 18 Sep 2017 07:39:21 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1abcfaca-3af0-efcf-d577-c3c5cb39e8fe@amsat.org>","References":"<1505494753-10837-1-git-send-email-sundeep.lkml@gmail.com>\n\t<1505494753-10837-3-git-send-email-sundeep.lkml@gmail.com>\n\t<2c6a4136-fb80-2000-940c-1df5e718cbf1@amsat.org>\n\t\n\t\n\t\n\t<6947945c-6b04-dce0-9010-b3350df0f151@amsat.org>\n\t\n\t<1abcfaca-3af0-efcf-d577-c3c5cb39e8fe@amsat.org>","From":"Peter Maydell ","Date":"Mon, 18 Sep 2017 15:39:00 +0100","Message-ID":"","To":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::231","Subject":"Re: [Qemu-devel] [Qemu devel v9 PATCH 2/5] msf2: Microsemi\n\tSmartfusion2 System Register block","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Francis ,\n\tPeter Crosthwaite ,\n\tqemu-arm , QEMU Developers , \n\tsundeep subbaraya ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]