Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/813814/?format=api
{ "id": 813814, "url": "http://patchwork.ozlabs.org/api/patches/813814/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170914125756.14836-2-shameerali.kolothum.thodi@huawei.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170914125756.14836-2-shameerali.kolothum.thodi@huawei.com>", "list_archive_url": null, "date": "2017-09-14T12:57:52", "name": "[v7,1/5] Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon erratum 161010801", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "13e71fa4ff32bd0bae9d2790868b1d66ec3c9ecd", "submitter": { "id": 70507, "url": "http://patchwork.ozlabs.org/api/people/70507/?format=api", "name": "Shameerali Kolothum Thodi", "email": "shameerali.kolothum.thodi@huawei.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170914125756.14836-2-shameerali.kolothum.thodi@huawei.com/mbox/", "series": [ { "id": 3093, "url": "http://patchwork.ozlabs.org/api/series/3093/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=3093", "date": "2017-09-14T12:57:51", "name": "iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI)", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/3093/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/813814/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/813814/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xtJYY4r9jz9sPt\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tThu, 14 Sep 2017 23:00:49 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751316AbdINNAs (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tThu, 14 Sep 2017 09:00:48 -0400", "from szxga04-in.huawei.com ([45.249.212.190]:6478 \"EHLO\n\tszxga04-in.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751133AbdINNAr (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Thu, 14 Sep 2017 09:00:47 -0400", "from 172.30.72.58 (EHLO DGGEMS413-HUB.china.huawei.com)\n\t([172.30.72.58])\n\tby dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DHF34305; Thu, 14 Sep 2017 21:00:44 +0800 (CST)", "from S00345302A-PC.china.huawei.com (10.212.247.163) by\n\tDGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP\n\tServer id 14.3.301.0; Thu, 14 Sep 2017 21:00:35 +0800" ], "From": "Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>", "To": "<lorenzo.pieralisi@arm.com>, <marc.zyngier@arm.com>,\n\t<sudeep.holla@arm.com>, <will.deacon@arm.com>,\n\t<robin.murphy@arm.com>, <joro@8bytes.org>, <mark.rutland@arm.com>,\n\t<hanjun.guo@linaro.org>", "CC": "<gabriele.paoloni@huawei.com>, <john.garry@huawei.com>,\n\t<iommu@lists.linux-foundation.org>,\n\t<linux-arm-kernel@lists.infradead.org>, \n\t<linux-acpi@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<devel@acpica.org>, <linuxarm@huawei.com>,\n\t<wangzhou1@hisilicon.com>, <guohanjun@huawei.com>,\n\tShameer Kolothum <shameerali.kolothum.thodi@huawei.com>", "Subject": "[PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon\n\terratum 161010801", "Date": "Thu, 14 Sep 2017 13:57:52 +0100", "Message-ID": "<20170914125756.14836-2-shameerali.kolothum.thodi@huawei.com>", "X-Mailer": "git-send-email 2.12.0.windows.1", "In-Reply-To": "<20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com>", "References": "<20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.212.247.163]", "X-CFilter-Loop": "Reflected", "X-Mirapoint-Virus-RAPID-Raw": "score=unknown(0),\n\trefid=str=0001.0A090206.59BA7D7C.011C, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32", "X-Mirapoint-Loop-Id": "314c5d550487ad0133a819442a53b2b4", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "From: John Garry <john.garry@huawei.com>\n\nThe HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms\nhip06/hip07 to support the SMMU mappings for MSI transactions.\n\nOn these platforms, GICv3 ITS translator is presented with the deviceID\nby extending the MSI payload data to 64 bits to include the deviceID.\nHence, the PCIe controller on this platforms has to differentiate the MSI\npayload against other DMA payload and has to modify the MSI payload.\nThis basically makes it difficult for this platforms to have a SMMU\ntranslation for MSI.\n\nThis patch adds a SMMUv3 binding to flag that the SMMU breaks msi\ntranslation at ITS.\n\nAlso, the arm64 silicon errata is updated with this same erratum.\n\nSigned-off-by: John Garry <john.garry@huawei.com>\nSigned-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>\n---\n Documentation/arm64/silicon-errata.txt | 1 +\n Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 3 +++\n 2 files changed, 4 insertions(+)", "diff": "diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt\nindex 66e8ce1..02816b1 100644\n--- a/Documentation/arm64/silicon-errata.txt\n+++ b/Documentation/arm64/silicon-errata.txt\n@@ -70,6 +70,7 @@ stable kernels.\n | | | | |\n | Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |\n | Hisilicon | Hip0{6,7} | #161010701 | N/A |\n+| Hisilicon | Hip0{6,7} | #161010801 | N/A |\n | | | | |\n | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |\n | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |\ndiff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\nindex c9abbf3..1f5f7f9 100644\n--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\n+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\n@@ -55,6 +55,9 @@ the PCIe specification.\n - hisilicon,broken-prefetch-cmd\n : Avoid sending CMD_PREFETCH_* commands to the SMMU.\n \n+- hisilicon,broken-untranslated-msi\n+ : Reserve ITS HW region to avoid translating msi.\n+\n - cavium,cn9900-broken-page1-regspace\n : Replaces all page 1 offsets used for EVTQ_PROD/CONS,\n \t\t PRIQ_PROD/CONS register access with page 0 offsets.\n", "prefixes": [ "v7", "1/5" ] }