[{"id":1771114,"web_url":"http://patchwork.ozlabs.org/comment/1771114/","msgid":"<20170919145314.2irmqpsfneeydupo@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-19T14:53:14","subject":"Re: [PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for\n\tHiSilicon erratum 161010801","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Thu, Sep 14, 2017 at 01:57:52PM +0100, Shameer Kolothum wrote:\n> From: John Garry <john.garry@huawei.com>\n> \n> The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms\n> hip06/hip07 to support the SMMU mappings for MSI transactions.\n> \n> On these platforms, GICv3 ITS translator is presented with the deviceID\n> by extending the MSI payload data to 64 bits to include the deviceID.\n> Hence, the PCIe controller on this platforms has to differentiate the MSI\n> payload against other DMA payload and has to modify the MSI payload.\n> This basically makes it difficult for this platforms to have a SMMU\n> translation for MSI.\n> \n> This patch adds a SMMUv3 binding to flag that the SMMU breaks msi\n> translation at ITS.\n> \n> Also, the arm64 silicon errata is updated with this same erratum.\n> \n> Signed-off-by: John Garry <john.garry@huawei.com>\n> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>\n> ---\n>  Documentation/arm64/silicon-errata.txt                  | 1 +\n>  Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 3 +++\n>  2 files changed, 4 insertions(+)\n> \n> diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt\n> index 66e8ce1..02816b1 100644\n> --- a/Documentation/arm64/silicon-errata.txt\n> +++ b/Documentation/arm64/silicon-errata.txt\n> @@ -70,6 +70,7 @@ stable kernels.\n>  |                |                 |                 |                             |\n>  | Hisilicon      | Hip0{5,6,7}     | #161010101      | HISILICON_ERRATUM_161010101 |\n>  | Hisilicon      | Hip0{6,7}       | #161010701      | N/A                         |\n> +| Hisilicon      | Hip0{6,7}       | #161010801      | N/A                         |\n>  |                |                 |                 |                             |\n>  | Qualcomm Tech. | Falkor v1       | E1003           | QCOM_FALKOR_ERRATUM_1003    |\n>  | Qualcomm Tech. | Falkor v1       | E1009           | QCOM_FALKOR_ERRATUM_1009    |\n> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\n> index c9abbf3..1f5f7f9 100644\n> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\n> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\n> @@ -55,6 +55,9 @@ the PCIe specification.\n>  - hisilicon,broken-prefetch-cmd\n>                      : Avoid sending CMD_PREFETCH_* commands to the SMMU.\n>  \n> +- hisilicon,broken-untranslated-msi\n> +                    : Reserve ITS HW region to avoid translating msi.\n> +\n\nThis should be determined from the compatible string. Continuing to add \nproperties for each errata doesn't scale.\n\n>  - cavium,cn9900-broken-page1-regspace\n>                      : Replaces all page 1 offsets used for EVTQ_PROD/CONS,\n>  \t\t      PRIQ_PROD/CONS register access with page 0 offsets.\n> -- \n> 1.9.1\n> \n> \n> --\n> To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n> the body of a message to majordomo@vger.kernel.org\n> More majordomo info at  http://vger.kernel.org/majordomo-info.html\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at  http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"<devicetree-owner@vger.kernel.org>","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxQq26jPLz9sBZ\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tWed, 20 Sep 2017 00:53:18 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1750862AbdISOxR (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tTue, 19 Sep 2017 10:53:17 -0400","from mail-it0-f66.google.com ([209.85.214.66]:34791 \"EHLO\n\tmail-it0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750828AbdISOxQ (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Tue, 19 Sep 2017 10:53:16 -0400","by mail-it0-f66.google.com with SMTP id o200so2537550itg.1;\n\tTue, 19 Sep 2017 07:53:15 -0700 (PDT)","from localhost (rrcs-67-78-118-34.sw.biz.rr.com. [67.78.118.34])\n\tby smtp.gmail.com with ESMTPSA id\n\tu97sm392543ota.50.2017.09.19.07.53.14\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 19 Sep 2017 07:53:14 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=eZKnRZ2xTEK19mmBECydVnV7DnkeTm0Vg57qCZ2Bw1U=;\n\tb=dxcmF16hIoWkb8nDz076NEvGlrKKYNxqkSSH4glzn3WS2tTdr4MObMDlImsRitkvVT\n\tq6rzZcfdwtOlqqlwVGuqEKuMTzhruRj1ElgaiyhvOhr4Xda5apePHKPkTZTNY71Tgsix\n\tA7fxhvJe2z9K31VJfC9wzW3V2c+4M5cLQiIrtCXa6aK/XQtEeZB4LdcY1s4KvjPNQ0U+\n\tpibtkPVu0D7Clz2OWTABU+FuN+cFOHajOyCvf/xbmzi3C8ku9s4ZroogcBmuyMvi/YAN\n\t7GfOnPXWJHu36o50L1qv2KMEY8uaJkyBKPdqTL+k1lNedETwfiEU3h3fOHJnrEo9vQzR\n\t6Kcw==","X-Gm-Message-State":"AHPjjUj5O8uugv9lUeZn3v07DGAkvAvVD3FkONmjIDRuAoUoS51lQ9ft\n\tsexgjIHnDhyh2sZSym8xTw==","X-Google-Smtp-Source":"AOwi7QB31Hw5DhnBAmvTbWo7RfGIswzp61UwfG5gO2BlzbNREwFQeppGx+lQxp7N7V8uVK7OIBkyiA==","X-Received":"by 10.202.79.13 with SMTP id d13mr1674370oib.189.1505832795447; \n\tTue, 19 Sep 2017 07:53:15 -0700 (PDT)","Date":"Tue, 19 Sep 2017 09:53:14 -0500","From":"Rob Herring <robh@kernel.org>","To":"Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>","Cc":"lorenzo.pieralisi@arm.com, marc.zyngier@arm.com,\n\tsudeep.holla@arm.com, will.deacon@arm.com, robin.murphy@arm.com,\n\tjoro@8bytes.org, mark.rutland@arm.com, hanjun.guo@linaro.org,\n\tgabriele.paoloni@huawei.com, john.garry@huawei.com,\n\tiommu@lists.linux-foundation.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org,\n\tdevicetree@vger.kernel.org, devel@acpica.org, linuxarm@huawei.com,\n\twangzhou1@hisilicon.com, guohanjun@huawei.com","Subject":"Re: [PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for\n\tHiSilicon erratum 161010801","Message-ID":"<20170919145314.2irmqpsfneeydupo@rob-hp-laptop>","References":"<20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com>\n\t<20170914125756.14836-2-shameerali.kolothum.thodi@huawei.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170914125756.14836-2-shameerali.kolothum.thodi@huawei.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<devicetree.vger.kernel.org>","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1771182,"web_url":"http://patchwork.ozlabs.org/comment/1771182/","msgid":"<5FC3163CFD30C246ABAA99954A238FA838411AD3@FRAEML521-MBX.china.huawei.com>","list_archive_url":null,"date":"2017-09-19T16:09:33","subject":"RE: [PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for\n\tHiSilicon erratum 161010801","submitter":{"id":70507,"url":"http://patchwork.ozlabs.org/api/people/70507/","name":"Shameerali Kolothum Thodi","email":"shameerali.kolothum.thodi@huawei.com"},"content":"> -----Original Message-----\n> From: Rob Herring [mailto:robh@kernel.org]\n> Sent: Tuesday, September 19, 2017 3:53 PM\n> To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>\n> Cc: lorenzo.pieralisi@arm.com; marc.zyngier@arm.com;\n> sudeep.holla@arm.com; will.deacon@arm.com; robin.murphy@arm.com;\n> joro@8bytes.org; mark.rutland@arm.com; hanjun.guo@linaro.org; Gabriele\n> Paoloni <gabriele.paoloni@huawei.com>; John Garry\n> <john.garry@huawei.com>; iommu@lists.linux-foundation.org; linux-arm-\n> kernel@lists.infradead.org; linux-acpi@vger.kernel.org;\n> devicetree@vger.kernel.org; devel@acpica.org; Linuxarm\n> <linuxarm@huawei.com>; Wangzhou (B) <wangzhou1@hisilicon.com>;\n> Guohanjun (Hanjun Guo) <guohanjun@huawei.com>\n> Subject: Re: [PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for\n> HiSilicon erratum 161010801\n> \n> On Thu, Sep 14, 2017 at 01:57:52PM +0100, Shameer Kolothum wrote:\n> > From: John Garry <john.garry@huawei.com>\n> >\n> > The HiSilicon erratum 161010801 describes the limitation of HiSilicon\n> platforms\n> > hip06/hip07 to support the SMMU mappings for MSI transactions.\n> >\n> > On these platforms, GICv3 ITS translator is presented with the deviceID\n> > by extending the MSI payload data to 64 bits to include the deviceID.\n> > Hence, the PCIe controller on this platforms has to differentiate the MSI\n> > payload against other DMA payload and has to modify the MSI payload.\n> > This basically makes it difficult for this platforms to have a SMMU\n> > translation for MSI.\n> >\n> > This patch adds a SMMUv3 binding to flag that the SMMU breaks msi\n> > translation at ITS.\n> >\n> > Also, the arm64 silicon errata is updated with this same erratum.\n> >\n> > Signed-off-by: John Garry <john.garry@huawei.com>\n> > Signed-off-by: Shameer Kolothum\n> <shameerali.kolothum.thodi@huawei.com>\n[...]\n> > --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\n> > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\n> > @@ -55,6 +55,9 @@ the PCIe specification.\n> >  - hisilicon,broken-prefetch-cmd\n> >                      : Avoid sending CMD_PREFETCH_* commands to the SMMU.\n> >\n> > +- hisilicon,broken-untranslated-msi\n> > +                    : Reserve ITS HW region to avoid translating msi.\n> > +\n> \n> This should be determined from the compatible string. Continuing to add\n> properties for each errata doesn't scale.\n\nOk. I think the suggestion here is to follow the arm-smmu.c (SMMUv1/v2) \ndriver way of implementing the errata. As you might have noticed,  the \nSMMUv3 driver dt errata framework depends on properties  and this will\nchange the way errata is implemented in the driver now.\n\nHi Will/Robin,\nCould you please take a look and let us know your thoughts on changing\nthe SMMUv3 dt errata implementation to version/model/compatible string\nframework for this quirk.\n\nThanks,\nShameer\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at  http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"<devicetree-owner@vger.kernel.org>","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxSXD1f6Zz9sMN\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tWed, 20 Sep 2017 02:10:36 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751098AbdISQKe convert rfc822-to-8bit (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tTue, 19 Sep 2017 12:10:34 -0400","from lhrrgout.huawei.com ([194.213.3.17]:35688 \"EHLO\n\tlhrrgout.huawei.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750972AbdISQKd (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Tue, 19 Sep 2017 12:10:33 -0400","from 172.18.7.190 (EHLO lhreml704-cah.china.huawei.com)\n\t([172.18.7.190])\n\tby lhrrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued)\n\twith ESMTP id DVU64325; Tue, 19 Sep 2017 16:09:49 +0000 (GMT)","from FRAEML702-CAH.china.huawei.com (10.206.14.33) by\n\tlhreml704-cah.china.huawei.com (10.201.108.45) with Microsoft SMTP\n\tServer (TLS) id 14.3.301.0; Tue, 19 Sep 2017 17:09:42 +0100","from FRAEML521-MBX.china.huawei.com ([169.254.1.161]) by\n\tfraeml702-cah.china.huawei.com ([10.206.14.33]) with mapi id\n\t14.03.0301.000; Tue, 19 Sep 2017 18:09:34 +0200"],"From":"Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>","To":"Rob Herring <robh@kernel.org>","CC":"\"lorenzo.pieralisi@arm.com\" <lorenzo.pieralisi@arm.com>,\n\t\"marc.zyngier@arm.com\" <marc.zyngier@arm.com>,\n\t\"sudeep.holla@arm.com\" <sudeep.holla@arm.com>,\n\t\"will.deacon@arm.com\" <will.deacon@arm.com>,\n\t\"robin.murphy@arm.com\" <robin.murphy@arm.com>,\n\t\"joro@8bytes.org\" <joro@8bytes.org>,\n\t\"mark.rutland@arm.com\" <mark.rutland@arm.com>,\n\t\"hanjun.guo@linaro.org\" <hanjun.guo@linaro.org>,\n\tGabriele Paoloni <gabriele.paoloni@huawei.com>,\n\tJohn Garry <john.garry@huawei.com>,\n\t\"iommu@lists.linux-foundation.org\" <iommu@lists.linux-foundation.org>,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t<linux-arm-kernel@lists.infradead.org>,\n\t\"linux-acpi@vger.kernel.org\" <linux-acpi@vger.kernel.org>,\n\t\"devicetree@vger.kernel.org\" <devicetree@vger.kernel.org>,\n\t\"devel@acpica.org\" <devel@acpica.org>, Linuxarm <linuxarm@huawei.com>,\n\t\"Wangzhou (B)\" <wangzhou1@hisilicon.com>,\n\t\"Guohanjun (Hanjun Guo)\" <guohanjun@huawei.com>","Subject":"RE: [PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for\n\tHiSilicon erratum 161010801","Thread-Topic":"[PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for\n\tHiSilicon erratum 161010801","Thread-Index":"AQHTLVl7i0VgSrSDgkWVkk8hYI0WSKK8MdAAgAAvcLA=","Date":"Tue, 19 Sep 2017 16:09:33 +0000","Message-ID":"<5FC3163CFD30C246ABAA99954A238FA838411AD3@FRAEML521-MBX.china.huawei.com>","References":"<20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com>\n\t<20170914125756.14836-2-shameerali.kolothum.thodi@huawei.com>\n\t<20170919145314.2irmqpsfneeydupo@rob-hp-laptop>","In-Reply-To":"<20170919145314.2irmqpsfneeydupo@rob-hp-laptop>","Accept-Language":"en-GB, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.203.177.212]","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"8BIT","MIME-Version":"1.0","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A020202.59C1414F.0053, ss=1, re=0.000, recu=0.000,\n\treip=0.000, \n\tcl=1, cld=1, fgs=0, ip=169.254.1.161,\n\tso=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"696153915bf86c269f6cf8efa13f28b4","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<devicetree.vger.kernel.org>","X-Mailing-List":"devicetree@vger.kernel.org"}}]