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{
    "id": 813666,
    "url": "http://patchwork.ozlabs.org/api/patches/813666/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1505343714-22359-1-git-send-email-vdumpa@nvidia.com/",
    "project": {
        "id": 21,
        "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api",
        "name": "Linux Tegra Development",
        "link_name": "linux-tegra",
        "list_id": "linux-tegra.vger.kernel.org",
        "list_email": "linux-tegra@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1505343714-22359-1-git-send-email-vdumpa@nvidia.com>",
    "list_archive_url": null,
    "date": "2017-09-13T23:01:54",
    "name": "arm64: tegra: Add SMMU node for Tegra186",
    "commit_ref": null,
    "pull_url": null,
    "state": "deferred",
    "archived": false,
    "hash": "906fe002098e92e09c428de5e7cf1b783dc5a349",
    "submitter": {
        "id": 72332,
        "url": "http://patchwork.ozlabs.org/api/people/72332/?format=api",
        "name": "Krishna Reddy",
        "email": "vdumpa@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/1505343714-22359-1-git-send-email-vdumpa@nvidia.com/mbox/",
    "series": [
        {
            "id": 2996,
            "url": "http://patchwork.ozlabs.org/api/series/2996/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=2996",
            "date": "2017-09-13T23:01:54",
            "name": "arm64: tegra: Add SMMU node for Tegra186",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/2996/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/813666/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/813666/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-tegra-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)",
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsy0D2cGdz9sxR\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 14 Sep 2017 09:04:12 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751308AbdIMXEL (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tWed, 13 Sep 2017 19:04:11 -0400",
            "from hqemgate14.nvidia.com ([216.228.121.143]:11869 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751148AbdIMXEK (ORCPT\n\t<rfc822;linux-tegra@vger.kernel.org>);\n\tWed, 13 Sep 2017 19:04:10 -0400",
            "from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com\n\tid <B59b9b9600002>; Wed, 13 Sep 2017 16:04:00 -0700",
            "from HQMAIL101.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tWed, 13 Sep 2017 16:03:59 -0700",
            "from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com\n\t(172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 13 Sep 2017 23:01:59 +0000",
            "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com\n\t(172.18.146.10) with Microsoft SMTP Server id 15.0.1293.2 via\n\tFrontend Transport; Wed, 13 Sep 2017 23:01:59 +0000",
            "from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.186.11]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150)\n\tid <B59b9b8e70000>; Wed, 13 Sep 2017 16:01:59 -0700"
        ],
        "X-PGP-Universal": "processed;\n\tby hqpgpgate102.nvidia.com on Wed, 13 Sep 2017 16:03:59 -0700",
        "From": "Krishna Reddy <vdumpa@nvidia.com>",
        "To": "<robh+dt@kernel.org>, <mark.rutland@arm.com>,\n\t<catalin.marinas@arm.com>, <will.deacon@arm.com>,\n\t<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<vdumpa@nvidia.com>, <josephl@nvidia.com>, <acourbot@nvidia.com>,\n\t<mperttunen@nvidia.com>, <devicetree@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>",
        "Subject": "[PATCH] arm64: tegra: Add SMMU node for Tegra186",
        "Date": "Wed, 13 Sep 2017 16:01:54 -0700",
        "Message-ID": "<1505343714-22359-1-git-send-email-vdumpa@nvidia.com>",
        "X-Mailer": "git-send-email 2.1.4",
        "X-NVConfidentiality": "public",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "Sender": "linux-tegra-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-tegra.vger.kernel.org>",
        "X-Mailing-List": "linux-tegra@vger.kernel.org"
    },
    "content": "Add the DT node for ARM SMMU on Tegra186.\n\nSigned-off-by: Krishna Reddy <vdumpa@nvidia.com>\n---\n arch/arm64/boot/dts/nvidia/tegra186.dtsi | 73 ++++++++++++++++++++++++++++++++\n 1 file changed, 73 insertions(+)",
    "diff": "diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi\nindex 0b0552c9f7dd..e2c3ad203c93 100644\n--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi\n+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi\n@@ -355,6 +355,79 @@\n \t\tnvidia,bpmp = <&bpmp>;\n \t};\n \n+\tsmmu: iommu@12000000 {\n+\t\tcompatible = \"arm,mmu-500\";\n+\t\treg = <0 0x12000000 0 0x800000>;\n+\t\t#global-interrupts = <1>;\n+\t\tinterrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t#iommu-cells = <1>;\n+\t\tstream-match-mask = <0x7F80>;\n+\t};\n+\n \tgpu@17000000 {\n \t\tcompatible = \"nvidia,gp10b\";\n \t\treg = <0x0 0x17000000 0x0 0x1000000>,\n",
    "prefixes": []
}