[{"id":1771805,"web_url":"http://patchwork.ozlabs.org/comment/1771805/","msgid":"<16a3d9cb-eb74-7e1c-82e2-487d0ed9db8f@kapsi.fi>","list_archive_url":null,"date":"2017-09-20T12:46:14","subject":"Re: [PATCH] arm64: tegra: Add SMMU node for Tegra186","submitter":{"id":64745,"url":"http://patchwork.ozlabs.org/api/people/64745/","name":"Mikko Perttunen","email":"cyndis@kapsi.fi"},"content":"Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>\nTested-by: Mikko Perttunen <mperttunen@nvidia.com>\n\nTested to work with Host1x :)\n\nI noticed a slight difference with downstream where downstream has \nglobal interrupts 170 and 171 - but looks like the latter is for secure \nfaults which we should never get so this way seems more correct.\n\nThanks,\nMikko\n\nOn 14.09.2017 02:01, Krishna Reddy wrote:\n> Add the DT node for ARM SMMU on Tegra186.\n>\n> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>\n> ---\n>  arch/arm64/boot/dts/nvidia/tegra186.dtsi | 73 ++++++++++++++++++++++++++++++++\n>  1 file changed, 73 insertions(+)\n>\n> diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi\n> index 0b0552c9f7dd..e2c3ad203c93 100644\n> --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi\n> +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi\n> @@ -355,6 +355,79 @@\n>  \t\tnvidia,bpmp = <&bpmp>;\n>  \t};\n>\n> +\tsmmu: iommu@12000000 {\n> +\t\tcompatible = \"arm,mmu-500\";\n> +\t\treg = <0 0x12000000 0 0x800000>;\n> +\t\t#global-interrupts = <1>;\n> +\t\tinterrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,\n> +\t\t\t     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;\n> +\t\t#iommu-cells = <1>;\n> +\t\tstream-match-mask = <0x7F80>;\n> +\t};\n> +\n>  \tgpu@17000000 {\n>  \t\tcompatible = \"nvidia,gp10b\";\n>  \t\treg = <0x0 0x17000000 0x0 0x1000000>,\n>\n--\nTo unsubscribe from this list: send the line \"unsubscribe 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<rfc822;incoming@patchwork.ozlabs.org>);\n\tWed, 20 Sep 2017 08:46:21 -0400","from mail.kapsi.fi ([91.232.154.25]:35595 \"EHLO mail.kapsi.fi\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751680AbdITMqU (ORCPT <rfc822;linux-tegra@vger.kernel.org>);\n\tWed, 20 Sep 2017 08:46:20 -0400","from [62.209.167.43] (helo=[10.21.26.144])\n\tby mail.kapsi.fi with esmtpsa\n\t(TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.84_2)\n\t(envelope-from <cyndis@kapsi.fi>)\n\tid 1dueOM-0005NJ-OE; Wed, 20 Sep 2017 15:46:14 +0300"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kapsi.fi;\n\ts=20161220; \n\th=Content-Transfer-Encoding:Content-Type:In-Reply-To:MIME-Version:Date:Message-ID:From:References:To:Subject;\n\tbh=wEOgJAsy456TV7VyOBRUBrSpBcMuxr5lXF21iiN2sLo=; \n\tb=A8WJBTDlnCThhVDOPbs1fBhwtHLOSYqzeAnxZqlXckzyUQ8D/af/bFvAVVe+cFQATBG/l5dRA2B4xzY/WyDwsYZgctUPZLCLdMc8NA3sJ1ag/sn5WM9KaZGHa2rYCoaaJSsixqrlcqEnAIEY310zOZ+HtruaKL8LBHCD0VdpSJj1ed3JhKq4MQIFKuUB944ita7eIR/7kLWmkwwpJZPojNy+VcEyT9UVs9tsLxiDool8UnXGr04CJCVeLynTtUVURHNq2tnGzn23BRIwA17lspJhjKJ4AvWHkCUJdUR2Tkony5SWlzuPzXzik+ChAoiVY1X7eworFbczTwbJ4rbS2g==;","Subject":"Re: [PATCH] arm64: tegra: Add SMMU node for Tegra186","To":"Krishna Reddy <vdumpa@nvidia.com>, robh+dt@kernel.org,\n\tmark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com,\n\tthierry.reding@gmail.com, jonathanh@nvidia.com, josephl@nvidia.com,\n\tacourbot@nvidia.com, mperttunen@nvidia.com,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org","References":"<1505343714-22359-1-git-send-email-vdumpa@nvidia.com>","From":"Mikko Perttunen <cyndis@kapsi.fi>","Message-ID":"<16a3d9cb-eb74-7e1c-82e2-487d0ed9db8f@kapsi.fi>","Date":"Wed, 20 Sep 2017 15:46:14 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.2.0","MIME-Version":"1.0","In-Reply-To":"<1505343714-22359-1-git-send-email-vdumpa@nvidia.com>","Content-Type":"text/plain; charset=windows-1252; format=flowed","Content-Transfer-Encoding":"7bit","X-SA-Exim-Connect-IP":"62.209.167.43","X-SA-Exim-Mail-From":"cyndis@kapsi.fi","X-SA-Exim-Scanned":"No (on mail.kapsi.fi); SAEximRunCond expanded to false","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<linux-tegra.vger.kernel.org>","X-Mailing-List":"linux-tegra@vger.kernel.org"}}]