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GET /api/patches/813309/?format=api
{ "id": 813309, "url": "http://patchwork.ozlabs.org/api/patches/813309/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1505297379-12638-5-git-send-email-david.wu@rock-chips.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505297379-12638-5-git-send-email-david.wu@rock-chips.com>", "list_archive_url": null, "date": "2017-09-13T10:09:35", "name": "[U-Boot,4/8] clk: rockchip: Add Saradc clock support for rk3288", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "4cd5b63ef736b7b6849fd475f59da04538236211", "submitter": { "id": 68083, "url": "http://patchwork.ozlabs.org/api/people/68083/?format=api", "name": "David Wu", "email": "david.wu@rock-chips.com" }, "delegate": { "id": 69486, "url": "http://patchwork.ozlabs.org/api/users/69486/?format=api", "username": "ptomsich", "first_name": "Philipp", "last_name": "Tomsich", "email": "philipp.tomsich@theobroma-systems.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1505297379-12638-5-git-send-email-david.wu@rock-chips.com/mbox/", "series": [ { "id": 2866, "url": "http://patchwork.ozlabs.org/api/series/2866/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=2866", "date": "2017-09-13T10:09:31", "name": "Add rockchip Saradc support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2866/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/813309/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/813309/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsctb3dj7z9s9Y\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 20:13:11 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 286E5C22619; Wed, 13 Sep 2017 10:12:00 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 4D916C22605;\n\tWed, 13 Sep 2017 10:11:23 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid A55C5C225E7; Wed, 13 Sep 2017 10:11:10 +0000 (UTC)", "from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.134])\n\tby lists.denx.de (Postfix) with ESMTPS id 77481C225ED\n\tfor <u-boot@lists.denx.de>; Wed, 13 Sep 2017 10:11:06 +0000 (UTC)", "from david.wu?rock-chips.com (unknown [192.168.167.229])\n\tby lucky1.263xmail.com (Postfix) with ESMTP id 75E56F54;\n\tWed, 13 Sep 2017 18:11:03 +0800 (CST)", "from localhost.localdomain (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id 53BB4369;\n\tWed, 13 Sep 2017 18:11:01 +0800 (CST)", "from unknown (unknown [58.22.7.114])\n\tby smtp.263.net (Postfix) whith SMTP id 154176N9H7V;\n\tWed, 13 Sep 2017 18:11:03 +0800 (CST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No,\n\tscore=0.6 required=5.0 tests=RCVD_IN_SORBS_WEB autolearn=no\n\tautolearn_force=no version=3.4.0", "X-263anti-spam": "KSV:0;", "X-MAIL-GRAY": "1", "X-MAIL-DELIVERY": "0", "X-KSVirus-check": "0", "X-ABS-CHECKED": "4", "X-RL-SENDER": "david.wu@rock-chips.com", "X-FST-TO": "sjg@chromium.org", "X-SENDER-IP": "58.22.7.114", "X-LOGIN-NAME": "david.wu@rock-chips.com", "X-UNIQUE-TAG": "<10cdc10d71248c37e1cf722f9a781385>", "X-ATTACHMENT-NUM": "0", "X-SENDER": "wdc@rock-chips.com", "X-DNS-TYPE": "0", "From": "David Wu <david.wu@rock-chips.com>", "To": "sjg@chromium.org,\n\tphilipp.tomsich@theobroma-systems.com", "Date": "Wed, 13 Sep 2017 18:09:35 +0800", "Message-Id": "<1505297379-12638-5-git-send-email-david.wu@rock-chips.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505297379-12638-1-git-send-email-david.wu@rock-chips.com>", "References": "<1505297379-12638-1-git-send-email-david.wu@rock-chips.com>", "Cc": "huangtao@rock-chips.com, u-boot@lists.denx.de, zhangqing@rock-chips.com, \n\tlinux-rockchip@lists.infradead.org, p.marczak@samsung.com,\n\tDavid Wu <david.wu@rock-chips.com>, andy.yan@rock-chips.com,\n\tchenjh@rock-chips.com", "Subject": "[U-Boot] [PATCH 4/8] clk: rockchip: Add Saradc clock support for\n\trk3288", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Signed-off-by: David Wu <david.wu@rock-chips.com>\n---\n drivers/clk/rockchip/clk_rk3288.c | 45 +++++++++++++++++++++++++++++++++++++++\n 1 file changed, 45 insertions(+)", "diff": "diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c\nindex 478195b..29652b0 100644\n--- a/drivers/clk/rockchip/clk_rk3288.c\n+++ b/drivers/clk/rockchip/clk_rk3288.c\n@@ -111,6 +111,15 @@ enum {\n \tPERI_ACLK_DIV_SHIFT\t= 0,\n \tPERI_ACLK_DIV_MASK\t= 0x1f << PERI_ACLK_DIV_SHIFT,\n \n+\t/*\n+\t * CLKSEL24\n+\t * saradc_div_con:\n+\t * clk_saradc=24MHz/(saradc_div_con+1)\n+\t */\n+\tCLK_SARADC_DIV_CON_SHIFT\t= 8,\n+\tCLK_SARADC_DIV_CON_MASK\t\t= 0xff << CLK_SARADC_DIV_CON_SHIFT,\n+\tCLK_SARADC_DIV_CON_WIDTH\t= 8,\n+\n \tSOCSTS_DPLL_LOCK\t= 1 << 5,\n \tSOCSTS_APLL_LOCK\t= 1 << 6,\n \tSOCSTS_CPLL_LOCK\t= 1 << 7,\n@@ -131,6 +140,11 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);\n static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);\n static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);\n \n+static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)\n+{\n+\treturn (val >> shift) & ((1 << width) - 1);\n+}\n+\n static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,\n \t\t\t const struct pll_div *div)\n {\n@@ -634,6 +648,31 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,\n \treturn rockchip_spi_get_clk(cru, gclk_rate, periph);\n }\n \n+static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)\n+{\n+\tu32 div, val;\n+\n+\tval = readl(&cru->cru_clksel_con[24]);\n+\tdiv = extract_bits(val, CLK_SARADC_DIV_CON_WIDTH,\n+\t\t\t CLK_SARADC_DIV_CON_SHIFT);\n+\n+\treturn DIV_TO_RATE(OSC_HZ, div);\n+}\n+\n+static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)\n+{\n+\tint src_clk_div;\n+\n+\tsrc_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;\n+\tassert(src_clk_div < 128);\n+\n+\trk_clrsetreg(&cru->cru_clksel_con[24],\n+\t\t CLK_SARADC_DIV_CON_MASK,\n+\t\t src_clk_div << CLK_SARADC_DIV_CON_SHIFT);\n+\n+\treturn rockchip_saradc_get_clk(cru);\n+}\n+\n static ulong rk3288_clk_get_rate(struct clk *clk)\n {\n \tstruct rk3288_clk_priv *priv = dev_get_priv(clk->dev);\n@@ -666,6 +705,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)\n \t\treturn gclk_rate;\n \tcase PCLK_PWM:\n \t\treturn PD_BUS_PCLK_HZ;\n+\tcase SCLK_SARADC:\n+\t\tnew_rate = rockchip_saradc_get_clk(priv->cru);\n+\t\tbreak;\n \tdefault:\n \t\treturn -ENOENT;\n \t}\n@@ -756,6 +798,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)\n \t\tnew_rate = rate;\n \t\tbreak;\n #endif\n+\tcase SCLK_SARADC:\n+\t\tnew_rate = rockchip_saradc_set_clk(priv->cru, rate);\n+\t\tbreak;\n \tdefault:\n \t\treturn -ENOENT;\n \t}\n", "prefixes": [ "U-Boot", "4/8" ] }