[{"id":1767761,"web_url":"http://patchwork.ozlabs.org/comment/1767761/","msgid":"<806B0139-A811-47EE-A217-FFB05F9C2042@theobroma-systems.com>","list_archive_url":null,"date":"2017-09-13T10:24:18","subject":"Re: [U-Boot] [PATCH 4/8] clk: rockchip: Add Saradc clock support\n\tfor rk3288","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> On 13 Sep 2017, at 12:09, David Wu wrote:\n> \n\nPlease add a commit message.\n\n> Signed-off-by: David Wu \n\nReviewed-by: Philipp Tomsich \n\nSee above and below for requested changes.\n\n> ---\n> drivers/clk/rockchip/clk_rk3288.c | 45 +++++++++++++++++++++++++++++++++++++++\n> 1 file changed, 45 insertions(+)\n> \n> diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c\n> index 478195b..29652b0 100644\n> --- a/drivers/clk/rockchip/clk_rk3288.c\n> +++ b/drivers/clk/rockchip/clk_rk3288.c\n> @@ -111,6 +111,15 @@ enum {\n> \tPERI_ACLK_DIV_SHIFT\t= 0,\n> \tPERI_ACLK_DIV_MASK\t= 0x1f << PERI_ACLK_DIV_SHIFT,\n> \n> +\t/*\n> +\t * CLKSEL24\n> +\t * saradc_div_con:\n> +\t * clk_saradc=24MHz/(saradc_div_con+1)\n> +\t */\n> +\tCLK_SARADC_DIV_CON_SHIFT\t= 8,\n> +\tCLK_SARADC_DIV_CON_MASK\t\t= 0xff << CLK_SARADC_DIV_CON_SHIFT,\n> +\tCLK_SARADC_DIV_CON_WIDTH\t= 8,\n> +\n> \tSOCSTS_DPLL_LOCK\t= 1 << 5,\n> \tSOCSTS_APLL_LOCK\t= 1 << 6,\n> \tSOCSTS_CPLL_LOCK\t= 1 << 7,\n> @@ -131,6 +140,11 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);\n> static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);\n> static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);\n> \n> +static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)\n> +{\n> +\treturn (val >> shift) & ((1 << width) - 1);\n> +}\n\nPlease reuse what’s already available in include/bitfield.h.\nThis also applies to all call-sites for extract_bits below: they should directly use the already existing function.\n\n> +\n> static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,\n> \t\t\t const struct pll_div *div)\n> {\n> @@ -634,6 +648,31 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,\n> \treturn rockchip_spi_get_clk(cru, gclk_rate, periph);\n> }\n> \n> +static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)\n> +{\n> +\tu32 div, val;\n> +\n> +\tval = readl(&cru->cru_clksel_con[24]);\n> +\tdiv = extract_bits(val, CLK_SARADC_DIV_CON_WIDTH,\n> +\t\t\t CLK_SARADC_DIV_CON_SHIFT);\n> +\n> +\treturn DIV_TO_RATE(OSC_HZ, div);\n> +}\n> +\n> +static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)\n> +{\n> +\tint src_clk_div;\n> +\n> +\tsrc_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;\n> +\tassert(src_clk_div < 128);\n> +\n> +\trk_clrsetreg(&cru->cru_clksel_con[24],\n> +\t\t CLK_SARADC_DIV_CON_MASK,\n> +\t\t src_clk_div << CLK_SARADC_DIV_CON_SHIFT);\n> +\n> +\treturn rockchip_saradc_get_clk(cru);\n> +}\n> +\n> static ulong rk3288_clk_get_rate(struct clk *clk)\n> {\n> \tstruct rk3288_clk_priv *priv = dev_get_priv(clk->dev);\n> @@ -666,6 +705,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)\n> \t\treturn gclk_rate;\n> \tcase PCLK_PWM:\n> \t\treturn PD_BUS_PCLK_HZ;\n> +\tcase SCLK_SARADC:\n> +\t\tnew_rate = rockchip_saradc_get_clk(priv->cru);\n> +\t\tbreak;\n> \tdefault:\n> \t\treturn -ENOENT;\n> \t}\n> @@ -756,6 +798,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)\n> \t\tnew_rate = rate;\n> \t\tbreak;\n> #endif\n> +\tcase SCLK_SARADC:\n> +\t\tnew_rate = rockchip_saradc_set_clk(priv->cru, rate);\n> +\t\tbreak;\n> \tdefault:\n> \t\treturn -ENOENT;\n> \t}\n> -- \n> 2.7.4\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsd7x5Wjlz9s76\n\tfor ;\n\tWed, 13 Sep 2017 20:24:45 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 664E8C22520; Wed, 13 Sep 2017 10:24:33 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 381AAC21DAE;\n\tWed, 13 Sep 2017 10:24:31 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 2A71EC222D5; Wed, 13 Sep 2017 10:24:30 +0000 (UTC)","from mail.theobroma-systems.com (vegas.theobroma-systems.com\n\t[144.76.126.164])\n\tby lists.denx.de (Postfix) with ESMTPS id E4A7EC21DAE\n\tfor ; Wed, 13 Sep 2017 10:24:29 +0000 (UTC)","from 89-104-28-141.customer.bnet.at ([89.104.28.141]:58355\n\thelo=[192.168.2.129]) by mail.theobroma-systems.com with esmtpsa\n\t(TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80)\n\t(envelope-from )\n\tid 1ds4qC-0002Ea-4B; Wed, 13 Sep 2017 12:24:20 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"*","X-Spam-Status":"No, score=1.0 required=5.0 tests=HK_NAME_DR autolearn=no\n\tautolearn_force=no version=3.4.0","Mime-Version":"1.0 (Mac OS X Mail 10.3 \\(3273\\))","From":"\"Dr. Philipp Tomsich\" ","In-Reply-To":"<1505297379-12638-5-git-send-email-david.wu@rock-chips.com>","Date":"Wed, 13 Sep 2017 12:24:18 +0200","Message-Id":"<806B0139-A811-47EE-A217-FFB05F9C2042@theobroma-systems.com>","References":"<1505297379-12638-1-git-send-email-david.wu@rock-chips.com>\n\t<1505297379-12638-5-git-send-email-david.wu@rock-chips.com>","To":"David Wu ","X-Mailer":"Apple Mail (2.3273)","Cc":"huangtao@rock-chips.com, u-boot@lists.denx.de, zhangqing@rock-chips.com, \n\tlinux-rockchip@lists.infradead.org, p.marczak@samsung.com,\n\tandy.yan@rock-chips.com, chenjh@rock-chips.com","Subject":"Re: [U-Boot] [PATCH 4/8] clk: rockchip: Add Saradc clock support\n\tfor rk3288","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1767763,"web_url":"http://patchwork.ozlabs.org/comment/1767763/","msgid":"","list_archive_url":null,"date":"2017-09-13T10:26:46","subject":"Re: [U-Boot] [PATCH 4/8] clk: rockchip: Add Saradc clock support\n\tfor rk3288","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> On 13 Sep 2017, at 12:09, David Wu wrote:\n> \n\nCommit message?\n\n> Signed-off-by: David Wu \n\nReviewed-by: Philipp Tomsich \n\nSee above and below for requested changes.\n\n> ---\n> drivers/clk/rockchip/clk_rk3288.c | 45 +++++++++++++++++++++++++++++++++++++++\n> 1 file changed, 45 insertions(+)\n> \n> diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c\n> index 478195b..29652b0 100644\n> --- a/drivers/clk/rockchip/clk_rk3288.c\n> +++ b/drivers/clk/rockchip/clk_rk3288.c\n> @@ -111,6 +111,15 @@ enum {\n> \tPERI_ACLK_DIV_SHIFT\t= 0,\n> \tPERI_ACLK_DIV_MASK\t= 0x1f << PERI_ACLK_DIV_SHIFT,\n> \n> +\t/*\n> +\t * CLKSEL24\n> +\t * saradc_div_con:\n> +\t * clk_saradc=24MHz/(saradc_div_con+1)\n> +\t */\n> +\tCLK_SARADC_DIV_CON_SHIFT\t= 8,\n> +\tCLK_SARADC_DIV_CON_MASK\t\t= 0xff << CLK_SARADC_DIV_CON_SHIFT,\n> +\tCLK_SARADC_DIV_CON_WIDTH\t= 8,\n> +\n> \tSOCSTS_DPLL_LOCK\t= 1 << 5,\n> \tSOCSTS_APLL_LOCK\t= 1 << 6,\n> \tSOCSTS_CPLL_LOCK\t= 1 << 7,\n> @@ -131,6 +140,11 @@ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);\n> static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);\n> static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);\n> \n> +static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)\n> +{\n> +\treturn (val >> shift) & ((1 << width) - 1);\n> +}\n\nSame comments apply as for patch 3/8.\n\n> +\n> static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id,\n> \t\t\t const struct pll_div *div)\n> {\n> @@ -634,6 +648,31 @@ static ulong rockchip_spi_set_clk(struct rk3288_cru *cru, uint gclk_rate,\n> \treturn rockchip_spi_get_clk(cru, gclk_rate, periph);\n> }\n> \n> +static ulong rockchip_saradc_get_clk(struct rk3288_cru *cru)\n> +{\n> +\tu32 div, val;\n> +\n> +\tval = readl(&cru->cru_clksel_con[24]);\n> +\tdiv = extract_bits(val, CLK_SARADC_DIV_CON_WIDTH,\n> +\t\t\t CLK_SARADC_DIV_CON_SHIFT);\n> +\n> +\treturn DIV_TO_RATE(OSC_HZ, div);\n> +}\n> +\n> +static ulong rockchip_saradc_set_clk(struct rk3288_cru *cru, uint hz)\n> +{\n> +\tint src_clk_div;\n> +\n> +\tsrc_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;\n> +\tassert(src_clk_div < 128);\n> +\n> +\trk_clrsetreg(&cru->cru_clksel_con[24],\n> +\t\t CLK_SARADC_DIV_CON_MASK,\n> +\t\t src_clk_div << CLK_SARADC_DIV_CON_SHIFT);\n> +\n> +\treturn rockchip_saradc_get_clk(cru);\n> +}\n> +\n> static ulong rk3288_clk_get_rate(struct clk *clk)\n> {\n> \tstruct rk3288_clk_priv *priv = dev_get_priv(clk->dev);\n> @@ -666,6 +705,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)\n> \t\treturn gclk_rate;\n> \tcase PCLK_PWM:\n> \t\treturn PD_BUS_PCLK_HZ;\n> +\tcase SCLK_SARADC:\n> +\t\tnew_rate = rockchip_saradc_get_clk(priv->cru);\n> +\t\tbreak;\n> \tdefault:\n> \t\treturn -ENOENT;\n> \t}\n> @@ -756,6 +798,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)\n> \t\tnew_rate = rate;\n> \t\tbreak;\n> #endif\n> +\tcase SCLK_SARADC:\n> +\t\tnew_rate = rockchip_saradc_set_clk(priv->cru, rate);\n> +\t\tbreak;\n> \tdefault:\n> \t\treturn -ENOENT;\n> \t}\n> -- \n> 2.7.4\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Wed, 13 Sep 2017 12:26:47 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"*","X-Spam-Status":"No, score=1.0 required=5.0 tests=HK_NAME_DR autolearn=no\n\tautolearn_force=no version=3.4.0","Mime-Version":"1.0 (Mac OS X Mail 10.3 \\(3273\\))","From":"\"Dr. Philipp Tomsich\" ","In-Reply-To":"<1505297379-12638-5-git-send-email-david.wu@rock-chips.com>","Date":"Wed, 13 Sep 2017 12:26:46 +0200","Message-Id":"","References":"<1505297379-12638-1-git-send-email-david.wu@rock-chips.com>\n\t<1505297379-12638-5-git-send-email-david.wu@rock-chips.com>","To":"David Wu ","X-Mailer":"Apple Mail (2.3273)","Cc":"huangtao@rock-chips.com, u-boot@lists.denx.de, zhangqing@rock-chips.com, \n\tlinux-rockchip@lists.infradead.org, p.marczak@samsung.com,\n\tandy.yan@rock-chips.com, chenjh@rock-chips.com","Subject":"Re: [U-Boot] [PATCH 4/8] clk: rockchip: Add Saradc clock support\n\tfor rk3288","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1768126,"web_url":"http://patchwork.ozlabs.org/comment/1768126/","msgid":"","list_archive_url":null,"date":"2017-09-13T20:07:41","subject":"Re: [U-Boot] [U-Boot,\n\t4/8] clk: rockchip: Add Saradc clock support for rk3288","submitter":{"id":53488,"url":"http://patchwork.ozlabs.org/api/people/53488/","name":"Philipp Tomsich","email":"philipp.tomsich@theobroma-systems.com"},"content":"> Signed-off-by: David Wu \n> Reviewed-by: Philipp Tomsich \n> Reviewed-by: Philipp Tomsich \n> ---\n> drivers/clk/rockchip/clk_rk3288.c | 45 +++++++++++++++++++++++++++++++++++++++\n> 1 file changed, 45 insertions(+)\n> \n\nAcked-by: Philipp Tomsich ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Wed, 13 Sep 2017 22:07:41 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0","MIME-Version":"1.0","From":"Philipp Tomsich ","To":"David Wu ","In-Reply-To":"<1505297379-12638-5-git-send-email-david.wu@rock-chips.com>","References":"<1505297379-12638-5-git-send-email-david.wu@rock-chips.com>","Message-Id":"","Date":"Wed, 13 Sep 2017 22:07:41 +0200","Cc":"huangtao@rock-chips.com, linux-rockchip@lists.infradead.org,\n\tzhangqing@rock-chips.com, u-boot@lists.denx.de, p.marczak@samsung.com,\n\tDavid Wu , andy.yan@rock-chips.com,\n\tchenjh@rock-chips.com","Subject":"Re: [U-Boot] [U-Boot,\n\t4/8] clk: rockchip: Add Saradc clock support for rk3288","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; 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