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GET /api/patches/813137/?format=api
{ "id": 813137, "url": "http://patchwork.ozlabs.org/api/patches/813137/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1505267666-9982-1-git-send-email-uboot@andestech.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505267666-9982-1-git-send-email-uboot@andestech.com>", "list_archive_url": null, "date": "2017-09-13T01:54:26", "name": "[U-Boot,2/3] nds32: ftmac100 support cache enable.", "commit_ref": "e336b73d8ae06dbcc532d1833d7a5567babecca8", "pull_url": null, "state": "accepted", "archived": false, "hash": "b6be87e7bbb5920cc6e46f5e4304d680f58e619a", "submitter": { "id": 28639, "url": "http://patchwork.ozlabs.org/api/people/28639/?format=api", "name": "Andes", "email": "uboot@andestech.com" }, "delegate": { "id": 20174, "url": "http://patchwork.ozlabs.org/api/users/20174/?format=api", "username": "Andes", "first_name": "Andes", "last_name": "", "email": "uboot@andestech.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1505267666-9982-1-git-send-email-uboot@andestech.com/mbox/", "series": [ { "id": 2798, "url": "http://patchwork.ozlabs.org/api/series/2798/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=2798", "date": "2017-09-13T01:53:42", "name": "[U-Boot,1/3] nds32: ftmac100: support cache enable.", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2798/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/813137/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/813137/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xsQLx6Ql1z9t30\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 12:18:33 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 64236C2229F; Wed, 13 Sep 2017 02:18:29 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 6706FC22300;\n\tWed, 13 Sep 2017 02:18:26 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 4E36CC222E5; Wed, 13 Sep 2017 02:18:16 +0000 (UTC)", "from ATCSQR.andestech.com (exmail.andestech.com [59.124.169.137])\n\tby lists.denx.de (Postfix) with ESMTPS id 811A6C22243\n\tfor <u-boot@lists.denx.de>; Wed, 13 Sep 2017 02:18:15 +0000 (UTC)", "from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222])\n\tby ATCSQR.andestech.com with ESMTP id v8D2CJI5033189;\n\tWed, 13 Sep 2017 10:12:19 +0800 (GMT-8)\n\t(envelope-from uboot@andestech.com)", "from app09.andestech.com (10.0.4.97) by ATCPCS16.andestech.com\n\t(10.0.1.222) with Microsoft SMTP Server id 14.3.123.3;\n\tWed, 13 Sep 2017 10:17:55 +0800" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "From": "Andes <uboot@andestech.com>", "To": "<u-boot@lists.denx.de>, <wd@denx.de>, <dzu@denx.de>", "Date": "Wed, 13 Sep 2017 09:54:26 +0800", "Message-ID": "<1505267666-9982-1-git-send-email-uboot@andestech.com>", "X-Mailer": "git-send-email 1.7.9.5", "MIME-Version": "1.0", "X-Originating-IP": "[10.0.4.97]", "X-DNSRBL": "", "X-MAIL": "ATCSQR.andestech.com v8D2CJI5033189", "Subject": "[U-Boot] [PATCH 2/3] nds32: ftmac100 support cache enable.", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: rick <rick@andestech.com>\n\nEnable cache and ftmac100 performance can be improved.\n\nSigned-off-by: rick <rick@andestech.com>\n---\n arch/nds32/cpu/n1213/start.S | 29 ++++++++++++++++++++++++++++-\n arch/nds32/include/asm/io.h | 21 +++++++++++++++++++++\n include/configs/adp-ae3xx.h | 3 +--\n include/configs/adp-ag101p.h | 3 +--\n 4 files changed, 51 insertions(+), 5 deletions(-)", "diff": "diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S\nindex f9f9999..0d98d03 100644\n--- a/arch/nds32/cpu/n1213/start.S\n+++ b/arch/nds32/cpu/n1213/start.S\n@@ -119,19 +119,46 @@ set_ivb:\n \t/* set IVIC, vector size: 4 bytes, base: 0x0 */\n \tmtsr\t$r0, $ivb\n /*\n- * MMU_CTL NTC0 Cacheable/Write-Back\n+ * MMU_CTL NTC0 Non-cacheable\n */\n+\tli\t$r0, ~0x6\n+\tmfsr\t$r1, $mr0\n+\tand\t$r1, $r1, $r0\n+\tmtsr\t$r1, $mr0\n+\n \tli\t$r0, ~0x3\n \tmfsr\t$r1, $mr8\n \tand\t$r1, $r1, $r0\n \tmtsr\t$r1, $mr8\n #if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF))\n+/*\n+ * MMU_CTL NTC0 Cacheable/Write-Back\n+ */\n \tli\t$r0, 0x4\n \tmfsr\t$r1, $mr0\n \tor\t$r1, $r1, $r0\n \tmtsr\t$r1, $mr0\n #endif\n \n+#ifndef CONFIG_SYS_DCACHE_OFF\n+#ifdef CONFIG_ARCH_MAP_SYSMEM\n+/*\n+ * MMU_CTL NTC1 Non-cacheable\n+ */\n+\tli\t$r0, ~0x18\n+\tmfsr\t$r1, $mr0\n+\tand\t$r1, $r1, $r0\n+\tmtsr\t$r1, $mr0\n+/*\n+ * MMU_CTL NTM1 mapping for partition 0\n+ */\n+\tli\t$r0, ~0x6000\n+\tmfsr\t$r1, $mr0\n+\tand\t$r1, $r1, $r0\n+\tmtsr\t$r1, $mr0\n+#endif\n+#endif\n+\n #if !defined(CONFIG_SYS_ICACHE_OFF)\n \tli\t$r0, 0x1\n \tmfsr\t$r1, $mr8\ndiff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h\nindex b2c4d0e..e8ee961 100644\n--- a/arch/nds32/include/asm/io.h\n+++ b/arch/nds32/include/asm/io.h\n@@ -48,6 +48,27 @@ static inline void sync(void)\n #define MAP_WRBACK\t(0)\n #define MAP_WRTHROUGH\t(0)\n \n+#ifdef CONFIG_ARCH_MAP_SYSMEM\n+static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)\n+{\n+\tif(paddr <PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE)\n+\tpaddr = paddr | 0x40000000;\n+\treturn (void *)(uintptr_t)paddr;\n+}\n+\n+static inline void *unmap_sysmem(const void *vaddr)\n+{\n+\tphys_addr_t paddr = (phys_addr_t)vaddr;\n+\tpaddr = paddr & ~0x40000000;\n+\treturn (void *)(uintptr_t)paddr;\n+}\n+\n+static inline phys_addr_t map_to_sysmem(const void *ptr)\n+{\n+\treturn (phys_addr_t)(uintptr_t)ptr;\n+}\n+#endif\n+\n static inline void *\n map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)\n {\ndiff --git a/include/configs/adp-ae3xx.h b/include/configs/adp-ae3xx.h\nindex cef1edd..fc04934 100644\n--- a/include/configs/adp-ae3xx.h\n+++ b/include/configs/adp-ae3xx.h\n@@ -23,8 +23,7 @@\n #define CONFIG_CMDLINE_EDITING\n #define CONFIG_PANIC_HANG\n \n-#define CONFIG_SYS_ICACHE_OFF\n-#define CONFIG_SYS_DCACHE_OFF\n+#define CONFIG_ARCH_MAP_SYSMEM\n \n #define CONFIG_BOOTP_SEND_HOSTNAME\n #define CONFIG_BOOTP_SERVERIP\ndiff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h\nindex f966278..a96213c 100644\n--- a/include/configs/adp-ag101p.h\n+++ b/include/configs/adp-ag101p.h\n@@ -22,8 +22,7 @@\n \n #define CONFIG_CMDLINE_EDITING\n \n-#define CONFIG_SYS_ICACHE_OFF\n-#define CONFIG_SYS_DCACHE_OFF\n+#define CONFIG_ARCH_MAP_SYSMEM\n \n #define CONFIG_BOOTP_SEND_HOSTNAME\n #define CONFIG_BOOTP_SERVERIP\n", "prefixes": [ "U-Boot", "2/3" ] }