From patchwork Wed Sep 13 01:53:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 813136 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xsQLG3KJXz9rxm for ; Wed, 13 Sep 2017 12:17:58 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 19FCCC22228; Wed, 13 Sep 2017 02:17:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 371B2C221B3; Wed, 13 Sep 2017 02:17:51 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 39878C22228; Wed, 13 Sep 2017 02:17:49 +0000 (UTC) Received: from ATCSQR.andestech.com (exmail.andestech.com [59.124.169.137]) by lists.denx.de (Postfix) with ESMTPS id B2D6FC222B4 for ; Wed, 13 Sep 2017 02:17:47 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id v8D2Bn5s033132; Wed, 13 Sep 2017 10:11:49 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.4.97) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Wed, 13 Sep 2017 10:17:24 +0800 From: Andes To: , , Date: Wed, 13 Sep 2017 09:53:42 +0800 Message-ID: <1505267622-9947-1-git-send-email-uboot@andestech.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-Originating-IP: [10.0.4.97] X-DNSRBL: X-MAIL: ATCSQR.andestech.com v8D2Bn5s033132 Subject: [U-Boot] [PATCH 1/3] nds32: ftmac100: support cache enable. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: rick Add cache inval and flush when rx and tx. Signed-off-by: rick --- drivers/net/ftmac100.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index f231e6b..4e45f00 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -79,7 +79,6 @@ static int _ftmac100_init(struct ftmac100_data *priv, unsigned char enetaddr[6]) struct ftmac100_rxdes *rxdes = priv->rxdes; unsigned int maccr; int i; - debug ("%s()\n", __func__); ftmac100_reset(priv); @@ -156,7 +155,6 @@ static int __ftmac100_recv(struct ftmac100_data *priv) unsigned short rxlen; curr_des = &priv->rxdes[priv->rx_index]; - if (curr_des->rxdes0 & FTMAC100_RXDES0_RXDMA_OWN) return 0; @@ -169,7 +167,7 @@ static int __ftmac100_recv(struct ftmac100_data *priv) } rxlen = FTMAC100_RXDES0_RFL (curr_des->rxdes0); - + invalidate_dcache_range(curr_des->rxdes2,curr_des->rxdes2+rxlen); debug ("%s(): RX buffer %d, %x received\n", __func__, priv->rx_index, rxlen); @@ -196,6 +194,7 @@ static int _ftmac100_send(struct ftmac100_data *priv, void *packet, int length) /* initiate a transmit sequence */ + flush_dcache_range((u32)packet,(u32)packet+length); curr_des->txdes2 = (unsigned int)packet; /* TXBUF_BADR */ curr_des->txdes1 &= FTMAC100_TXDES1_EDOTR; From patchwork Wed Sep 13 01:54:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andes X-Patchwork-Id: 813137 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xsQLx6Ql1z9t30 for ; Wed, 13 Sep 2017 12:18:33 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 64236C2229F; Wed, 13 Sep 2017 02:18:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6706FC22300; Wed, 13 Sep 2017 02:18:26 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4E36CC222E5; Wed, 13 Sep 2017 02:18:16 +0000 (UTC) Received: from ATCSQR.andestech.com (exmail.andestech.com [59.124.169.137]) by lists.denx.de (Postfix) with ESMTPS id 811A6C22243 for ; Wed, 13 Sep 2017 02:18:15 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id v8D2CJI5033189; Wed, 13 Sep 2017 10:12:19 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.4.97) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Wed, 13 Sep 2017 10:17:55 +0800 From: Andes To: , , Date: Wed, 13 Sep 2017 09:54:26 +0800 Message-ID: <1505267666-9982-1-git-send-email-uboot@andestech.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-Originating-IP: [10.0.4.97] X-DNSRBL: X-MAIL: ATCSQR.andestech.com v8D2CJI5033189 Subject: [U-Boot] [PATCH 2/3] nds32: ftmac100 support cache enable. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: rick Enable cache and ftmac100 performance can be improved. Signed-off-by: rick --- arch/nds32/cpu/n1213/start.S | 29 ++++++++++++++++++++++++++++- arch/nds32/include/asm/io.h | 21 +++++++++++++++++++++ include/configs/adp-ae3xx.h | 3 +-- include/configs/adp-ag101p.h | 3 +-- 4 files changed, 51 insertions(+), 5 deletions(-) diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index f9f9999..0d98d03 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -119,19 +119,46 @@ set_ivb: /* set IVIC, vector size: 4 bytes, base: 0x0 */ mtsr $r0, $ivb /* - * MMU_CTL NTC0 Cacheable/Write-Back + * MMU_CTL NTC0 Non-cacheable */ + li $r0, ~0x6 + mfsr $r1, $mr0 + and $r1, $r1, $r0 + mtsr $r1, $mr0 + li $r0, ~0x3 mfsr $r1, $mr8 and $r1, $r1, $r0 mtsr $r1, $mr8 #if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)) +/* + * MMU_CTL NTC0 Cacheable/Write-Back + */ li $r0, 0x4 mfsr $r1, $mr0 or $r1, $r1, $r0 mtsr $r1, $mr0 #endif +#ifndef CONFIG_SYS_DCACHE_OFF +#ifdef CONFIG_ARCH_MAP_SYSMEM +/* + * MMU_CTL NTC1 Non-cacheable + */ + li $r0, ~0x18 + mfsr $r1, $mr0 + and $r1, $r1, $r0 + mtsr $r1, $mr0 +/* + * MMU_CTL NTM1 mapping for partition 0 + */ + li $r0, ~0x6000 + mfsr $r1, $mr0 + and $r1, $r1, $r0 + mtsr $r1, $mr0 +#endif +#endif + #if !defined(CONFIG_SYS_ICACHE_OFF) li $r0, 0x1 mfsr $r1, $mr8 diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h index b2c4d0e..e8ee961 100644 --- a/arch/nds32/include/asm/io.h +++ b/arch/nds32/include/asm/io.h @@ -48,6 +48,27 @@ static inline void sync(void) #define MAP_WRBACK (0) #define MAP_WRTHROUGH (0) +#ifdef CONFIG_ARCH_MAP_SYSMEM +static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) +{ + if(paddr X-Patchwork-Id: 813142 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3xsQSt2WgZz9sNr for ; Wed, 13 Sep 2017 12:23:41 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id C4AB1C2206F; Wed, 13 Sep 2017 02:20:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 16430C22115; Wed, 13 Sep 2017 02:20:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4819AC22243; Wed, 13 Sep 2017 02:18:54 +0000 (UTC) Received: from ATCSQR.andestech.com (exmail.andestech.com [59.124.169.137]) by lists.denx.de (Postfix) with ESMTPS id 219C7C22304 for ; Wed, 13 Sep 2017 02:18:50 +0000 (UTC) Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id v8D2CtUr033225; Wed, 13 Sep 2017 10:12:55 +0800 (GMT-8) (envelope-from uboot@andestech.com) Received: from app09.andestech.com (10.0.4.97) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.123.3; Wed, 13 Sep 2017 10:18:29 +0800 From: Andes To: , , Date: Wed, 13 Sep 2017 09:54:59 +0800 Message-ID: <1505267699-10017-1-git-send-email-uboot@andestech.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-Originating-IP: [10.0.4.97] X-DNSRBL: X-MAIL: ATCSQR.andestech.com v8D2CtUr033225 Subject: [U-Boot] [PATCH 3/3] nds32: ftmac100: Fix write mac addr fail problem. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: rick After soft reset complete, write mac address immediately will fail. Add delay to work around this problem. Signed-off-by: rick --- drivers/net/ftmac100.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index 4e45f00..e64bf3d 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -40,7 +40,12 @@ static void ftmac100_reset(struct ftmac100_data *priv) writel (FTMAC100_MACCR_SW_RST, &ftmac100->maccr); while (readl (&ftmac100->maccr) & FTMAC100_MACCR_SW_RST) - ; + mdelay(1); + /* + * When soft reset complete, write mac address immediately maybe fail somehow + * Wait for a while can avoid this problem + */ + mdelay(1); } /*