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GET /api/patches/813005/?format=api
{ "id": 813005, "url": "http://patchwork.ozlabs.org/api/patches/813005/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-16-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505240046-11454-16-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-12T18:14:02", "name": "[15/19] nvic: Handle v8M changes in nvic_exec_prio()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c6a235c146c9e4f28ee8807cb483a9d0ce62f0f1", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-16-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 2751, "url": "http://patchwork.ozlabs.org/api/series/2751/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751", "date": "2017-09-12T18:13:53", "name": "ARMv8M: support security extn in the NVIC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2751/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/813005/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/813005/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsD0N5vNVz9s81\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 04:31:48 +1000 (AEST)", "from localhost ([::1]:38043 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drpyM-0003zR-TH\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:31:46 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:43595)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph6-0003Xk-R8\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:57 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph5-0006VV-TH\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:56 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37316)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1drph2-0006QF-5A; Tue, 12 Sep 2017 14:13:52 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgz-00019p-Lp; Tue, 12 Sep 2017 19:13:49 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 19:14:02 +0100", "Message-Id": "<1505240046-11454-16-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "References": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 15/19] nvic: Handle v8M changes in\n\tnvic_exec_prio()", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Update nvic_exec_prio() to support the v8M changes:\n * BASEPRI, FAULTMASK and PRIMASK are all banked\n * AIRCR.PRIS can affect NS priorities\n * AIRCR.BFHFNMINS affects FAULTMASK behaviour\n\nThese changes mean that it's no longer possible to\ndefinitely say that if FAULTMASK is set it overrides\nPRIMASK, and if PRIMASK is set it overrides BASEPRI\n(since if PRIMASK_NS is set and AIRCR.PRIS is set then\nwhether that 0x80 priority should take effect or the\npriority in BASEPRI_S depends on the value of BASEPRI_S,\nfor instance). So we switch to the same approach used\nby the pseudocode of working through BASEPRI, PRIMASK\nand FAULTMASK and overriding the previous values if\nneeded.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/intc/armv7m_nvic.c | 51 ++++++++++++++++++++++++++++++++++++++++++---------\n 1 file changed, 42 insertions(+), 9 deletions(-)", "diff": "diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex 91d2f33..b13327d 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -319,18 +319,51 @@ static void nvic_recompute_state(NVICState *s)\n static inline int nvic_exec_prio(NVICState *s)\n {\n CPUARMState *env = &s->cpu->env;\n- int running;\n+ int running = NVIC_NOEXC_PRIO;\n \n- if (env->v7m.faultmask[env->v7m.secure]) {\n- running = -1;\n- } else if (env->v7m.primask[env->v7m.secure]) {\n+ if (env->v7m.basepri[M_REG_NS] > 0) {\n+ running = exc_group_prio(s, env->v7m.basepri[M_REG_NS], M_REG_NS);\n+ }\n+\n+ if (env->v7m.basepri[M_REG_S] > 0) {\n+ int basepri = exc_group_prio(s, env->v7m.basepri[M_REG_S], M_REG_S);\n+ if (running > basepri) {\n+ running = basepri;\n+ }\n+ }\n+\n+ if (env->v7m.primask[M_REG_NS]) {\n+ if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {\n+ if (running > NVIC_NS_PRIO_LIMIT) {\n+ running = NVIC_NS_PRIO_LIMIT;\n+ }\n+ } else {\n+ running = 0;\n+ }\n+ }\n+\n+ if (env->v7m.primask[M_REG_S]) {\n running = 0;\n- } else if (env->v7m.basepri[env->v7m.secure] > 0) {\n- running = env->v7m.basepri[env->v7m.secure] &\n- nvic_gprio_mask(s, env->v7m.secure);\n- } else {\n- running = NVIC_NOEXC_PRIO; /* lower than any possible priority */\n }\n+\n+ if (env->v7m.faultmask[M_REG_NS]) {\n+ if (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) {\n+ running = -1;\n+ } else {\n+ if (env->v7m.aircr & R_V7M_AIRCR_PRIS_MASK) {\n+ if (running > NVIC_NS_PRIO_LIMIT) {\n+ running = NVIC_NS_PRIO_LIMIT;\n+ }\n+ } else {\n+ running = 0;\n+ }\n+ }\n+ }\n+\n+ if (env->v7m.faultmask[M_REG_S]) {\n+ running = (env->v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) ? -3 : -1;\n+ }\n+\n /* consider priority of active handler */\n return MIN(running, s->exception_prio);\n }\n", "prefixes": [ "15/19" ] }