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GET /api/patches/812999/?format=api
{ "id": 812999, "url": "http://patchwork.ozlabs.org/api/patches/812999/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-10-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505240046-11454-10-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-12T18:13:56", "name": "[09/19] nvic: Make set_pending and clear_pending take a secure parameter", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "03ba2523ffb3350dc985fad0c2724e26511ce009", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-10-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 2751, "url": "http://patchwork.ozlabs.org/api/series/2751/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751", "date": "2017-09-12T18:13:53", "name": "ARMv8M: support security extn in the NVIC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2751/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812999/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812999/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsCpd18NKz9s3T\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 04:23:20 +1000 (AEST)", "from localhost ([::1]:37994 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drpq9-0003YI-ND\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:23:18 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:43590)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph6-0003Xa-MJ\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:58 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph4-0006Tm-1E\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:56 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37292)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgx-0006Ln-GH; Tue, 12 Sep 2017 14:13:47 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgv-00016V-MS; Tue, 12 Sep 2017 19:13:45 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 19:13:56 +0100", "Message-Id": "<1505240046-11454-10-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "References": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 09/19] nvic: Make set_pending and clear_pending\n\ttake a secure parameter", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Make the armv7m_nvic_set_pending() and armv7m_nvic_clear_pending()\nfunctions take a bool indicating whether to pend the secure\nor non-secure version of a banked interrupt, and update the\ncallsites accordingly.\n\nIn most callsites we can simply pass the correct security\nstate in; in a couple of cases we use TODO comments to indicate\nthat we will return the code in a subsequent commit.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/cpu.h | 14 ++++++++++-\n hw/intc/armv7m_nvic.c | 64 ++++++++++++++++++++++++++++++++++++++-------------\n target/arm/helper.c | 24 +++++++++++--------\n hw/intc/trace-events | 4 ++--\n 4 files changed, 77 insertions(+), 29 deletions(-)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 7e661c8..7a93354 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -1463,7 +1463,19 @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)\n return true;\n }\n #endif\n-void armv7m_nvic_set_pending(void *opaque, int irq);\n+/**\n+ * armv7m_nvic_set_pending: mark the specified exception as pending\n+ * @opaque: the NVIC\n+ * @irq: the exception number to mark pending\n+ * @secure: false for non-banked exceptions or for the nonsecure\n+ * version of a banked exception, true for the secure version of a banked\n+ * exception.\n+ *\n+ * Marks the specified exception as pending. Note that we will assert()\n+ * if @secure is true and @irq does not specify one of the fixed set\n+ * of architecturally banked exceptions.\n+ */\n+void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);\n void armv7m_nvic_acknowledge_irq(void *opaque);\n /**\n * armv7m_nvic_complete_irq: complete specified interrupt or exception\ndiff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex fb824e6..852db11 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -384,31 +384,50 @@ static void nvic_irq_update(NVICState *s)\n qemu_set_irq(s->excpout, lvl);\n }\n \n-static void armv7m_nvic_clear_pending(void *opaque, int irq)\n+/**\n+ * armv7m_nvic_clear_pending: mark the specified exception as not pending\n+ * @opaque: the NVIC\n+ * @irq: the exception number to mark as not pending\n+ * @secure: false for non-banked exceptions or for the nonsecure\n+ * version of a banked exception, true for the secure version of a banked\n+ * exception.\n+ *\n+ * Marks the specified exception as not pending. Note that we will assert()\n+ * if @secure is true and @irq does not specify one of the fixed set\n+ * of architecturally banked exceptions.\n+ */\n+static void armv7m_nvic_clear_pending(void *opaque, int irq, bool secure)\n {\n NVICState *s = (NVICState *)opaque;\n VecInfo *vec;\n \n assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);\n \n- vec = &s->vectors[irq];\n- trace_nvic_clear_pending(irq, vec->enabled, vec->prio);\n+ if (secure) {\n+ assert(exc_is_banked(irq));\n+ vec = &s->sec_vectors[irq];\n+ } else {\n+ vec = &s->vectors[irq];\n+ }\n+ trace_nvic_clear_pending(irq, secure, vec->enabled, vec->prio);\n if (vec->pending) {\n vec->pending = 0;\n nvic_irq_update(s);\n }\n }\n \n-void armv7m_nvic_set_pending(void *opaque, int irq)\n+void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)\n {\n NVICState *s = (NVICState *)opaque;\n+ bool banked = exc_is_banked(irq);\n VecInfo *vec;\n \n assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);\n+ assert(!secure || banked);\n \n- vec = &s->vectors[irq];\n- trace_nvic_set_pending(irq, vec->enabled, vec->prio);\n+ vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];\n \n+ trace_nvic_set_pending(irq, secure, vec->enabled, vec->prio);\n \n if (irq >= ARMV7M_EXCP_HARD && irq < ARMV7M_EXCP_PENDSV) {\n /* If a synchronous exception is pending then it may be\n@@ -454,9 +473,20 @@ void armv7m_nvic_set_pending(void *opaque, int irq)\n \"(current priority %d)\\n\", irq, running);\n }\n \n- /* We can do the escalation, so we take HardFault instead */\n+ /* We can do the escalation, so we take HardFault instead.\n+ * If BFHFNMINS is set then we escalate to the banked HF for\n+ * the target security state of the original exception; otherwise\n+ * we take a Secure HardFault.\n+ */\n irq = ARMV7M_EXCP_HARD;\n- vec = &s->vectors[irq];\n+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&\n+ (secure ||\n+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) {\n+ vec = &s->sec_vectors[irq];\n+ } else {\n+ vec = &s->vectors[irq];\n+ }\n+ /* HF may be banked but there is only one shared HFSR */\n s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;\n }\n }\n@@ -551,7 +581,7 @@ static void set_irq_level(void *opaque, int n, int level)\n if (level != vec->level) {\n vec->level = level;\n if (level) {\n- armv7m_nvic_set_pending(s, n);\n+ armv7m_nvic_set_pending(s, n, false);\n }\n }\n }\n@@ -837,17 +867,17 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,\n }\n case 0xd04: /* Interrupt Control State. */\n if (value & (1 << 31)) {\n- armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);\n+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI, false);\n }\n if (value & (1 << 28)) {\n- armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);\n+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);\n } else if (value & (1 << 27)) {\n- armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV);\n+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_PENDSV, attrs.secure);\n }\n if (value & (1 << 26)) {\n- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);\n+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);\n } else if (value & (1 << 25)) {\n- armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK);\n+ armv7m_nvic_clear_pending(s, ARMV7M_EXCP_SYSTICK, attrs.secure);\n }\n break;\n case 0xd08: /* Vector Table Offset. */\n@@ -1093,7 +1123,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,\n {\n int excnum = (value & 0x1ff) + NVIC_FIRST_IRQ;\n if (excnum < s->num_irq) {\n- armv7m_nvic_set_pending(s, excnum);\n+ armv7m_nvic_set_pending(s, excnum, false);\n }\n break;\n }\n@@ -1495,8 +1525,10 @@ static void nvic_systick_trigger(void *opaque, int n, int level)\n /* SysTick just asked us to pend its exception.\n * (This is different from an external interrupt line's\n * behaviour.)\n+ * TODO: when we implement the banked systicks we must make\n+ * this pend the correct banked exception.\n */\n- armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);\n+ armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK, false);\n }\n }\n \ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex f4f2a87..b64acd8 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6306,7 +6306,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n * stack, directly take a usage fault on the current stack.\n */\n env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;\n- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);\n+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);\n v7m_exception_taken(cpu, excret);\n qemu_log_mask(CPU_LOG_INT, \"...taking UsageFault on existing \"\n \"stackframe: failed exception return integrity check\\n\");\n@@ -6345,8 +6345,11 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n * exception return excret specified then this is a UsageFault.\n */\n if (return_to_handler != arm_v7m_is_handler_mode(env)) {\n- /* Take an INVPC UsageFault by pushing the stack again. */\n- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);\n+ /* Take an INVPC UsageFault by pushing the stack again.\n+ * TODO: the v8M version of this code should target the\n+ * background state for this exception.\n+ */\n+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false);\n env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVPC_MASK;\n v7m_push_stack(cpu);\n v7m_exception_taken(cpu, excret);\n@@ -6406,20 +6409,20 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)\n handle it. */\n switch (cs->exception_index) {\n case EXCP_UDEF:\n- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);\n+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);\n env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK;\n break;\n case EXCP_NOCP:\n- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);\n+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);\n env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK;\n break;\n case EXCP_INVSTATE:\n- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);\n+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure);\n env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK;\n break;\n case EXCP_SWI:\n /* The PC already points to the next instruction. */\n- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);\n+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure);\n break;\n case EXCP_PREFETCH_ABORT:\n case EXCP_DATA_ABORT:\n@@ -6443,7 +6446,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)\n env->v7m.bfar);\n break;\n }\n- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS);\n+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);\n break;\n default:\n /* All other FSR values are either MPU faults or \"can't happen\n@@ -6463,7 +6466,8 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)\n env->v7m.mmfar[env->v7m.secure]);\n break;\n }\n- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);\n+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM,\n+ env->v7m.secure);\n break;\n }\n break;\n@@ -6480,7 +6484,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)\n return;\n }\n }\n- armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);\n+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false);\n break;\n case EXCP_IRQ:\n break;\ndiff --git a/hw/intc/trace-events b/hw/intc/trace-events\nindex 0b1fba3..94038b6 100644\n--- a/hw/intc/trace-events\n+++ b/hw/intc/trace-events\n@@ -173,8 +173,8 @@ nvic_set_prio(int irq, uint8_t prio) \"NVIC set irq %d priority %d\"\n nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) \"NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d\"\n nvic_escalate_prio(int irq, int irqprio, int runprio) \"NVIC escalating irq %d to HardFault: insufficient priority %d >= %d\"\n nvic_escalate_disabled(int irq) \"NVIC escalating irq %d to HardFault: disabled\"\n-nvic_set_pending(int irq, int en, int prio) \"NVIC set pending irq %d (enabled: %d priority %d)\"\n-nvic_clear_pending(int irq, int en, int prio) \"NVIC clear pending irq %d (enabled: %d priority %d)\"\n+nvic_set_pending(int irq, bool secure, int en, int prio) \"NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)\"\n+nvic_clear_pending(int irq, bool secure, int en, int prio) \"NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)\"\n nvic_set_pending_level(int irq) \"NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1\"\n nvic_acknowledge_irq(int irq, int prio) \"NVIC acknowledge IRQ: %d now active (prio %d)\"\n nvic_complete_irq(int irq) \"NVIC complete IRQ %d\"\n", "prefixes": [ "09/19" ] }