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GET /api/patches/812998/?format=api
{ "id": 812998, "url": "http://patchwork.ozlabs.org/api/patches/812998/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-2-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505240046-11454-2-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-12T18:13:48", "name": "[01/19] target/arm: Implement MSR/MRS access to NS banked registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "22469cbd60e838c7287d64d865ce7535d8c8cb40", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-2-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 2751, "url": "http://patchwork.ozlabs.org/api/series/2751/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751", "date": "2017-09-12T18:13:53", "name": "ARMv8M: support security extn in the NVIC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2751/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812998/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812998/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsCmR1LFNz9s3T\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 04:21:27 +1000 (AEST)", "from localhost ([::1]:37988 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drpoL-0001UM-4q\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:21:25 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:43397)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph2-0003Qz-13\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:53 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph0-0006RF-SQ\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:51 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37298)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgx-0006Mo-3w; Tue, 12 Sep 2017 14:13:47 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgq-00012z-9z; Tue, 12 Sep 2017 19:13:40 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 19:13:48 +0100", "Message-Id": "<1505240046-11454-2-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "References": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 01/19] target/arm: Implement MSR/MRS access to\n\tNS banked registers", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "In v8M the MSR and MRS instructions have extra register value\nencodings to allow secure code to access the non-secure banked\nversion of various special registers.\n\n(We don't implement the MSPLIM_NS or PSPLIM_NS aliases, because\nwe don't currently implement the stack limit registers at all.)\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/helper.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 110 insertions(+)", "diff": "diff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 4f41841..f4f2a87 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -8892,12 +8892,68 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)\n break;\n case 20: /* CONTROL */\n return env->v7m.control[env->v7m.secure];\n+ case 0x94: /* CONTROL_NS */\n+ /* We have to handle this here because unprivileged Secure code\n+ * can read the NS CONTROL register.\n+ */\n+ if (!env->v7m.secure) {\n+ return 0;\n+ }\n+ return env->v7m.control[M_REG_NS];\n }\n \n if (el == 0) {\n return 0; /* unprivileged reads others as zero */\n }\n \n+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {\n+ switch (reg) {\n+ case 0x88: /* MSP_NS */\n+ if (!env->v7m.secure) {\n+ return 0;\n+ }\n+ return env->v7m.other_ss_msp;\n+ case 0x89: /* PSP_NS */\n+ if (!env->v7m.secure) {\n+ return 0;\n+ }\n+ return env->v7m.other_ss_psp;\n+ case 0x90: /* PRIMASK_NS */\n+ if (!env->v7m.secure) {\n+ return 0;\n+ }\n+ return env->v7m.primask[M_REG_NS];\n+ case 0x91: /* BASEPRI_NS */\n+ if (!env->v7m.secure) {\n+ return 0;\n+ }\n+ return env->v7m.basepri[M_REG_NS];\n+ case 0x93: /* FAULTMASK_NS */\n+ if (!env->v7m.secure) {\n+ return 0;\n+ }\n+ return env->v7m.faultmask[M_REG_NS];\n+ case 0x98: /* SP_NS */\n+ {\n+ /* This gives the non-secure SP selected based on whether we're\n+ * currently in handler mode or not, using the NS CONTROL.SPSEL.\n+ */\n+ bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;\n+\n+ if (!env->v7m.secure) {\n+ return 0;\n+ }\n+ if (!arm_v7m_is_handler_mode(env) && spsel) {\n+ return env->v7m.other_ss_psp;\n+ } else {\n+ return env->v7m.other_ss_msp;\n+ }\n+ }\n+ default:\n+ break;\n+ }\n+ }\n+\n switch (reg) {\n case 8: /* MSP */\n return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) ?\n@@ -8936,6 +8992,60 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)\n return;\n }\n \n+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {\n+ switch (reg) {\n+ case 0x88: /* MSP_NS */\n+ if (!env->v7m.secure) {\n+ return;\n+ }\n+ env->v7m.other_ss_msp = val;\n+ return;\n+ case 0x89: /* PSP_NS */\n+ if (!env->v7m.secure) {\n+ return;\n+ }\n+ env->v7m.other_ss_psp = val;\n+ return;\n+ case 0x90: /* PRIMASK_NS */\n+ if (!env->v7m.secure) {\n+ return;\n+ }\n+ env->v7m.primask[M_REG_NS] = val & 1;\n+ return;\n+ case 0x91: /* BASEPRI_NS */\n+ if (!env->v7m.secure) {\n+ return;\n+ }\n+ env->v7m.basepri[M_REG_NS] = val & 0xff;\n+ return;\n+ case 0x93: /* FAULTMASK_NS */\n+ if (!env->v7m.secure) {\n+ return;\n+ }\n+ env->v7m.faultmask[M_REG_NS] = val & 1;\n+ return;\n+ case 0x98: /* SP_NS */\n+ {\n+ /* This gives the non-secure SP selected based on whether we're\n+ * currently in handler mode or not, using the NS CONTROL.SPSEL.\n+ */\n+ bool spsel = env->v7m.control[M_REG_NS] & R_V7M_CONTROL_SPSEL_MASK;\n+\n+ if (!env->v7m.secure) {\n+ return;\n+ }\n+ if (!arm_v7m_is_handler_mode(env) && spsel) {\n+ env->v7m.other_ss_psp = val;\n+ } else {\n+ env->v7m.other_ss_msp = val;\n+ }\n+ return;\n+ }\n+ default:\n+ break;\n+ }\n+ }\n+\n switch (reg) {\n case 0 ... 7: /* xPSR sub-fields */\n /* only APSR is actually writable */\n", "prefixes": [ "01/19" ] }