[{"id":1768233,"web_url":"http://patchwork.ozlabs.org/comment/1768233/","msgid":"<2a2c4292-cfcc-0dbd-d9fa-edbe56dfe639@linaro.org>","list_archive_url":null,"date":"2017-09-13T22:58:59","subject":"Re: [Qemu-devel] [PATCH 01/19] target/arm: Implement MSR/MRS access\n\tto NS banked registers","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 09/12/2017 11:13 AM, Peter Maydell wrote:\n> In v8M the MSR and MRS instructions have extra register value\n> encodings to allow secure code to access the non-secure banked\n> version of various special registers.\n> \n> (We don't implement the MSPLIM_NS or PSPLIM_NS aliases, because\n> we don't currently implement the stack limit registers at all.)\n> \n> Signed-off-by: Peter Maydell \n> ---\n> target/arm/helper.c | 110 ++++++++++++++++++++++++++++++++++++++++++++++++++++\n> 1 file changed, 110 insertions(+)\n\nReviewed-by: Richard Henderson \n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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