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GET /api/patches/812995/?format=api
{ "id": 812995, "url": "http://patchwork.ozlabs.org/api/patches/812995/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-20-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505240046-11454-20-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-12T18:14:06", "name": "[19/19] nvic: Support banked exceptions in acknowledge and complete", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d1484fbf6a034536d70f85a9f845ce7cef50cbe7", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-20-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 2751, "url": "http://patchwork.ozlabs.org/api/series/2751/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751", "date": "2017-09-12T18:13:53", "name": "ARMv8M: support security extn in the NVIC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2751/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812995/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812995/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsCm05fsRz9sP1\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 04:21:04 +1000 (AEST)", "from localhost ([::1]:37984 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drpny-0001Ac-RL\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:21:02 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:43661)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph9-0003bn-Jz\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:14:01 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph8-0006Wg-54\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:59 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37316)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1drph4-0006QF-4d; Tue, 12 Sep 2017 14:13:54 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1drph2-0001BU-I3; Tue, 12 Sep 2017 19:13:52 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 19:14:06 +0100", "Message-Id": "<1505240046-11454-20-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "References": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 19/19] nvic: Support banked exceptions in\n\tacknowledge and complete", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Update armv7m_nvic_acknowledge_irq() and armv7m_nvic_complete_irq()\nto handle banked exceptions:\n * acknowledge needs to use the correct vector, which may be\n in sec_vectors[]\n * acknowledge needs to return to its caller whether the\n exception should be taken to secure or non-secure state\n * complete needs its caller to tell it whether the exception\n being completed is a secure one or not\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/cpu.h | 15 +++++++++++++--\n hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++++------\n target/arm/helper.c | 8 +++++---\n hw/intc/trace-events | 4 ++--\n 4 files changed, 40 insertions(+), 13 deletions(-)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex 02be3ca..9c336bc 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -1476,18 +1476,29 @@ static inline bool armv7m_nvic_can_take_pending_exception(void *opaque)\n * of architecturally banked exceptions.\n */\n void armv7m_nvic_set_pending(void *opaque, int irq, bool secure);\n-void armv7m_nvic_acknowledge_irq(void *opaque);\n+/**\n+ * armv7m_nvic_acknowledge_irq: make highest priority pending exception active\n+ * @opaque: the NVIC\n+ *\n+ * Move the current highest priority pending exception from the pending\n+ * state to the active state, and update v7m.exception to indicate that\n+ * it is the exception currently being handled.\n+ *\n+ * Returns: true if exception should be taken to Secure state, false for NS\n+ */\n+bool armv7m_nvic_acknowledge_irq(void *opaque);\n /**\n * armv7m_nvic_complete_irq: complete specified interrupt or exception\n * @opaque: the NVIC\n * @irq: the exception number to complete\n+ * @secure: true if this exception was secure\n *\n * Returns: -1 if the irq was not active\n * 1 if completing this irq brought us back to base (no active irqs)\n * 0 if there is still an irq active after this one was completed\n * (Ignoring -1, this is the same as the RETTOBASE value before completion.)\n */\n-int armv7m_nvic_complete_irq(void *opaque, int irq);\n+int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure);\n /**\n * armv7m_nvic_raw_execution_priority: return the raw execution priority\n * @opaque: the NVIC\ndiff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex 9613990..078532a 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -586,24 +586,32 @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure)\n }\n \n /* Make pending IRQ active. */\n-void armv7m_nvic_acknowledge_irq(void *opaque)\n+bool armv7m_nvic_acknowledge_irq(void *opaque)\n {\n NVICState *s = (NVICState *)opaque;\n CPUARMState *env = &s->cpu->env;\n const int pending = s->vectpending;\n const int running = nvic_exec_prio(s);\n VecInfo *vec;\n+ bool targets_secure;\n \n assert(pending > ARMV7M_EXCP_RESET && pending < s->num_irq);\n \n- vec = &s->vectors[pending];\n+ if (s->vectpending_is_s_banked) {\n+ vec = &s->sec_vectors[pending];\n+ targets_secure = true;\n+ } else {\n+ vec = &s->vectors[pending];\n+ targets_secure = !exc_is_banked(s->vectpending) &&\n+ exc_targets_secure(s, s->vectpending);\n+ }\n \n assert(vec->enabled);\n assert(vec->pending);\n \n assert(s->vectpending_prio < running);\n \n- trace_nvic_acknowledge_irq(pending, s->vectpending_prio);\n+ trace_nvic_acknowledge_irq(pending, s->vectpending_prio, targets_secure);\n \n vec->active = 1;\n vec->pending = 0;\n@@ -611,9 +619,11 @@ void armv7m_nvic_acknowledge_irq(void *opaque)\n env->v7m.exception = s->vectpending;\n \n nvic_irq_update(s);\n+\n+ return targets_secure;\n }\n \n-int armv7m_nvic_complete_irq(void *opaque, int irq)\n+int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)\n {\n NVICState *s = (NVICState *)opaque;\n VecInfo *vec;\n@@ -621,9 +631,13 @@ int armv7m_nvic_complete_irq(void *opaque, int irq)\n \n assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);\n \n- vec = &s->vectors[irq];\n+ if (secure && exc_is_banked(irq)) {\n+ vec = &s->sec_vectors[irq];\n+ } else {\n+ vec = &s->vectors[irq];\n+ }\n \n- trace_nvic_complete_irq(irq);\n+ trace_nvic_complete_irq(irq, secure);\n \n if (!vec->active) {\n /* Tell the caller this was an illegal exception return */\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex b64acd8..8be78ea 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6218,6 +6218,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n bool return_to_sp_process = false;\n bool return_to_handler = false;\n bool rettobase = false;\n+ bool exc_secure = false;\n \n /* We can only get here from an EXCP_EXCEPTION_EXIT, and\n * gen_bx_excret() enforces the architectural rule\n@@ -6256,16 +6257,17 @@ static void do_v7m_exception_exit(ARMCPU *cpu)\n * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.)\n */\n if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {\n- int es = excret & R_V7M_EXCRET_ES_MASK;\n+ exc_secure = excret & R_V7M_EXCRET_ES_MASK;\n if (armv7m_nvic_raw_execution_priority(env->nvic) >= 0) {\n- env->v7m.faultmask[es] = 0;\n+ env->v7m.faultmask[exc_secure] = 0;\n }\n } else {\n env->v7m.faultmask[M_REG_NS] = 0;\n }\n }\n \n- switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) {\n+ switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception,\n+ exc_secure)) {\n case -1:\n /* attempt to exit an exception that isn't active */\n ufault = true;\ndiff --git a/hw/intc/trace-events b/hw/intc/trace-events\nindex 29bd308..b86f242 100644\n--- a/hw/intc/trace-events\n+++ b/hw/intc/trace-events\n@@ -176,8 +176,8 @@ nvic_escalate_disabled(int irq) \"NVIC escalating irq %d to HardFault: disabled\"\n nvic_set_pending(int irq, bool secure, int en, int prio) \"NVIC set pending irq %d secure-bank %d (enabled: %d priority %d)\"\n nvic_clear_pending(int irq, bool secure, int en, int prio) \"NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)\"\n nvic_set_pending_level(int irq) \"NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1\"\n-nvic_acknowledge_irq(int irq, int prio) \"NVIC acknowledge IRQ: %d now active (prio %d)\"\n-nvic_complete_irq(int irq) \"NVIC complete IRQ %d\"\n+nvic_acknowledge_irq(int irq, int prio, bool targets_secure) \"NVIC acknowledge IRQ: %d now active (prio %d targets_secure %d)\"\n+nvic_complete_irq(int irq, bool secure) \"NVIC complete IRQ %d (secure %d)\"\n nvic_set_irq_level(int irq, int level) \"NVIC external irq %d level set to %d\"\n nvic_sysreg_read(uint64_t addr, uint32_t value, unsigned size) \"NVIC sysreg read addr 0x%\" PRIx64 \" data 0x%\" PRIx32 \" size %u\"\n nvic_sysreg_write(uint64_t addr, uint32_t value, unsigned size) \"NVIC sysreg write addr 0x%\" PRIx64 \" data 0x%\" PRIx32 \" size %u\"\n", "prefixes": [ "19/19" ] }