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GET /api/patches/812987/?format=api
{ "id": 812987, "url": "http://patchwork.ozlabs.org/api/patches/812987/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-3-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505240046-11454-3-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-12T18:13:49", "name": "[02/19] nvic: Add banked exception states", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cde198856b3a295e0b0144c6f182d49d4d7ffaf4", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-3-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 2751, "url": "http://patchwork.ozlabs.org/api/series/2751/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751", "date": "2017-09-12T18:13:53", "name": "ARMv8M: support security extn in the NVIC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2751/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812987/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812987/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsCdF5GLFz9sNV\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 04:15:13 +1000 (AEST)", "from localhost ([::1]:37946 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drpiJ-000465-Gn\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:15:11 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:43235)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drpgx-0003M4-2t\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:49 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drpgv-0006N4-QE\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:47 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37276)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgs-0006IX-Mg; Tue, 12 Sep 2017 14:13:42 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgq-00013G-Tx; Tue, 12 Sep 2017 19:13:40 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 19:13:49 +0100", "Message-Id": "<1505240046-11454-3-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "References": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 02/19] nvic: Add banked exception states", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "For the v8M security extension, some exceptions must be banked\nbetween security states. Add the new vecinfo array which holds\nthe state for the banked exceptions and migrate it if the\nCPU the NVIC is attached to implements the security extension.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n include/hw/intc/armv7m_nvic.h | 14 +++++++++++++\n hw/intc/armv7m_nvic.c | 49 ++++++++++++++++++++++++++++++++++++++++++-\n 2 files changed, 62 insertions(+), 1 deletion(-)", "diff": "diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h\nindex 1a4cce7..317601e 100644\n--- a/include/hw/intc/armv7m_nvic.h\n+++ b/include/hw/intc/armv7m_nvic.h\n@@ -21,6 +21,8 @@\n \n /* Highest permitted number of exceptions (architectural limit) */\n #define NVIC_MAX_VECTORS 512\n+/* Number of internal exceptions */\n+#define NVIC_INTERNAL_VECTORS 16\n \n typedef struct VecInfo {\n /* Exception priorities can range from -3 to 255; only the unmodifiable\n@@ -41,6 +43,18 @@ typedef struct NVICState {\n ARMCPU *cpu;\n \n VecInfo vectors[NVIC_MAX_VECTORS];\n+ /* If the v8M security extension is implemented, some of the internal\n+ * exceptions are banked between security states (ie there exists both\n+ * a Secure and a NonSecure version of the exception and its state):\n+ * HardFault, MemManage, UsageFault, SVCall, PendSV, SysTick (R_PJHV)\n+ * The rest (including all the external exceptions) are not banked, though\n+ * they may be configurable to target either Secure or NonSecure state.\n+ * We store the secure exception state in sec_vectors[] for the banked\n+ * exceptions, and otherwise use only vectors[] (including for exceptions\n+ * like SecureFault that unconditionally target Secure state).\n+ * Entries in sec_vectors[] for non-banked exception numbers are unused.\n+ */\n+ VecInfo sec_vectors[NVIC_INTERNAL_VECTORS];\n uint32_t prigroup;\n \n /* vectpending and exception_prio are both cached state that can\ndiff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex d3e2056..694b9e0 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -47,7 +47,7 @@\n * For historical reasons QEMU tends to use \"interrupt\" and\n * \"exception\" more or less interchangeably.\n */\n-#define NVIC_FIRST_IRQ 16\n+#define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS\n #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)\n \n /* Effective running priority of the CPU when no exception is active\n@@ -1158,6 +1158,43 @@ static const VMStateDescription vmstate_VecInfo = {\n }\n };\n \n+static bool nvic_security_needed(void *opaque)\n+{\n+ NVICState *s = opaque;\n+\n+ return arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY);\n+}\n+\n+static int nvic_security_post_load(void *opaque, int version_id)\n+{\n+ NVICState *s = opaque;\n+ int i;\n+\n+ /* Check for out of range priority settings */\n+ if (s->sec_vectors[ARMV7M_EXCP_HARD].prio != -1) {\n+ return 1;\n+ }\n+ for (i = ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) {\n+ if (s->sec_vectors[i].prio & ~0xff) {\n+ return 1;\n+ }\n+ }\n+ return 0;\n+}\n+\n+static const VMStateDescription vmstate_nvic_security = {\n+ .name = \"nvic/m-security\",\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .needed = nvic_security_needed,\n+ .post_load = &nvic_security_post_load,\n+ .fields = (VMStateField[]) {\n+ VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,\n+ vmstate_VecInfo, VecInfo),\n+ VMSTATE_END_OF_LIST()\n+ }\n+};\n+\n static const VMStateDescription vmstate_nvic = {\n .name = \"armv7m_nvic\",\n .version_id = 4,\n@@ -1195,6 +1232,16 @@ static void armv7m_nvic_reset(DeviceState *dev)\n s->vectors[ARMV7M_EXCP_NMI].prio = -2;\n s->vectors[ARMV7M_EXCP_HARD].prio = -1;\n \n+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {\n+ s->sec_vectors[ARMV7M_EXCP_HARD].enabled = 1;\n+ s->sec_vectors[ARMV7M_EXCP_SVC].enabled = 1;\n+ s->sec_vectors[ARMV7M_EXCP_PENDSV].enabled = 1;\n+ s->sec_vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;\n+\n+ /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */\n+ s->sec_vectors[ARMV7M_EXCP_HARD].prio = -1;\n+ }\n+\n /* Strictly speaking the reset handler should be enabled.\n * However, we don't simulate soft resets through the NVIC,\n * and the reset vector should never be pended.\n", "prefixes": [ "02/19" ] }