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GET /api/patches/812986/?format=api
{ "id": 812986, "url": "http://patchwork.ozlabs.org/api/patches/812986/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-8-git-send-email-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1505240046-11454-8-git-send-email-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2017-09-12T18:13:54", "name": "[07/19] nvic: Implement NVIC_ITNS<n> registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "72be60ea8834b85441ce21e7be3d4efb9977d9d7", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-8-git-send-email-peter.maydell@linaro.org/mbox/", "series": [ { "id": 2751, "url": "http://patchwork.ozlabs.org/api/series/2751/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751", "date": "2017-09-12T18:13:53", "name": "ARMv8M: support security extn in the NVIC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2751/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812986/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812986/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsCdF1yR6z9s0g\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 04:15:13 +1000 (AEST)", "from localhost ([::1]:37945 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drpiI-00045s-WD\n\tfor incoming@patchwork.ozlabs.org; Tue, 12 Sep 2017 14:15:11 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:43418)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph2-0003Rj-I4\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:54 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <pm215@archaic.org.uk>) id 1drph0-0006R9-Sp\n\tfor qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:52 -0400", "from orth.archaic.org.uk ([2001:8b0:1d0::2]:37292)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgw-0006Ln-Fp; Tue, 12 Sep 2017 14:13:46 -0400", "from pm215 by orth.archaic.org.uk with local (Exim 4.89)\n\t(envelope-from <pm215@archaic.org.uk>)\n\tid 1drpgu-00015X-8t; Tue, 12 Sep 2017 19:13:44 +0100" ], "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-arm@nongnu.org,\n\tqemu-devel@nongnu.org", "Date": "Tue, 12 Sep 2017 19:13:54 +0100", "Message-Id": "<1505240046-11454-8-git-send-email-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "References": "<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2001:8b0:1d0::2", "Subject": "[Qemu-devel] [PATCH 07/19] nvic: Implement NVIC_ITNS<n> registers", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "patches@linaro.org", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "For v8M, the NVIC has a new set of registers per interrupt,\nNVIC_ITNS<n>. These determine whether the interrupt targets Secure\nor Non-secure state. Implement the register read/write code for\nthese, and make them cause NVIC_IABR, NVIC_ICER, NVIC_ISER,\nNVIC_ICPR, NVIC_IPR and NVIC_ISPR to RAZ/WI for non-secure\naccesses to fields corresponding to interrupts which are\nconfigured to target secure state.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n include/hw/intc/armv7m_nvic.h | 3 ++\n hw/intc/armv7m_nvic.c | 74 +++++++++++++++++++++++++++++++++++++++----\n 2 files changed, 70 insertions(+), 7 deletions(-)", "diff": "diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h\nindex e96e488..ac7997c 100644\n--- a/include/hw/intc/armv7m_nvic.h\n+++ b/include/hw/intc/armv7m_nvic.h\n@@ -58,6 +58,9 @@ typedef struct NVICState {\n /* The PRIGROUP field in AIRCR is banked */\n uint32_t prigroup[M_REG_NUM_BANKS];\n \n+ /* v8M NVIC_ITNS state (stored as a bool per bit) */\n+ bool itns[NVIC_MAX_VECTORS];\n+\n /* The following fields are all cached state that can be recalculated\n * from the vectors[] and sec_vectors[] arrays and the prigroup field:\n * - vectpending\ndiff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c\nindex edaf60c..b97dbe3 100644\n--- a/hw/intc/armv7m_nvic.c\n+++ b/hw/intc/armv7m_nvic.c\n@@ -423,6 +423,25 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)\n switch (offset) {\n case 4: /* Interrupt Control Type. */\n return ((s->num_irq - NVIC_FIRST_IRQ) / 32) - 1;\n+ case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */\n+ {\n+ int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;\n+ int i;\n+\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ return 0;\n+ }\n+ val = 0;\n+ for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {\n+ if (s->itns[startvec + i]) {\n+ val |= (1 << i);\n+ }\n+ }\n+ return val;\n+ }\n case 0xd00: /* CPUID Base. */\n return cpu->midr;\n case 0xd04: /* Interrupt Control State. */\n@@ -658,6 +677,23 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,\n ARMCPU *cpu = s->cpu;\n \n switch (offset) {\n+ case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */\n+ {\n+ int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ;\n+ int i;\n+\n+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) {\n+ goto bad_offset;\n+ }\n+ if (!attrs.secure) {\n+ break;\n+ }\n+ for (i = 0; i < 32 && startvec + i < s->num_irq; i++) {\n+ s->itns[startvec + i] = value & (1 << i);\n+ }\n+ nvic_irq_update(s);\n+ break;\n+ }\n case 0xd04: /* Interrupt Control State. */\n if (value & (1 << 31)) {\n armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);\n@@ -966,7 +1002,8 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,\n startvec = offset - 0x180 + NVIC_FIRST_IRQ; /* vector # */\n \n for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {\n- if (s->vectors[startvec + i].enabled) {\n+ if (s->vectors[startvec + i].enabled &&\n+ (attrs.secure || s->itns[startvec + i])) {\n val |= (1 << i);\n }\n }\n@@ -978,7 +1015,8 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,\n val = 0;\n startvec = offset - 0x280 + NVIC_FIRST_IRQ; /* vector # */\n for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {\n- if (s->vectors[startvec + i].pending) {\n+ if (s->vectors[startvec + i].pending &&\n+ (attrs.secure || s->itns[startvec + i])) {\n val |= (1 << i);\n }\n }\n@@ -988,7 +1026,8 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,\n startvec = offset - 0x300 + NVIC_FIRST_IRQ; /* vector # */\n \n for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {\n- if (s->vectors[startvec + i].active) {\n+ if (s->vectors[startvec + i].active &&\n+ (attrs.secure || s->itns[startvec + i])) {\n val |= (1 << i);\n }\n }\n@@ -998,7 +1037,9 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,\n startvec = offset - 0x400 + NVIC_FIRST_IRQ; /* vector # */\n \n for (i = 0; i < size && startvec + i < s->num_irq; i++) {\n- val |= s->vectors[startvec + i].prio << (8 * i);\n+ if (attrs.secure || s->itns[startvec + i]) {\n+ val |= s->vectors[startvec + i].prio << (8 * i);\n+ }\n }\n break;\n case 0xd18 ... 0xd23: /* System Handler Priority. */\n@@ -1055,7 +1096,8 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,\n startvec = 8 * (offset - 0x180) + NVIC_FIRST_IRQ;\n \n for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {\n- if (value & (1 << i)) {\n+ if (value & (1 << i) &&\n+ (attrs.secure || s->itns[startvec + i])) {\n s->vectors[startvec + i].enabled = setval;\n }\n }\n@@ -1072,7 +1114,8 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,\n startvec = 8 * (offset - 0x280) + NVIC_FIRST_IRQ; /* vector # */\n \n for (i = 0, end = size * 8; i < end && startvec + i < s->num_irq; i++) {\n- if (value & (1 << i)) {\n+ if (value & (1 << i) &&\n+ (attrs.secure || s->itns[startvec + i])) {\n s->vectors[startvec + i].pending = setval;\n }\n }\n@@ -1084,7 +1127,9 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,\n startvec = 8 * (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */\n \n for (i = 0; i < size && startvec + i < s->num_irq; i++) {\n- set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);\n+ if (attrs.secure || s->itns[startvec + i]) {\n+ set_prio(s, startvec + i, (value >> (i * 8)) & 0xff);\n+ }\n }\n nvic_irq_update(s);\n return MEMTX_OK;\n@@ -1223,6 +1268,7 @@ static const VMStateDescription vmstate_nvic_security = {\n VMSTATE_STRUCT_ARRAY(sec_vectors, NVICState, NVIC_INTERNAL_VECTORS, 1,\n vmstate_VecInfo, VecInfo),\n VMSTATE_UINT32(prigroup[M_REG_S], NVICState),\n+ VMSTATE_BOOL_ARRAY(itns, NVICState, NVIC_MAX_VECTORS),\n VMSTATE_END_OF_LIST()\n }\n };\n@@ -1284,6 +1330,20 @@ static void armv7m_nvic_reset(DeviceState *dev)\n s->vectpending = 0;\n s->vectpending_is_s_banked = false;\n s->vectpending_prio = NVIC_NOEXC_PRIO;\n+\n+ if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) {\n+ memset(s->itns, 0, sizeof(s->itns));\n+ } else {\n+ /* This state is constant and not guest accessible in a non-security\n+ * NVIC; we set the bits to true to avoid having to do a feature\n+ * bit check in the NVIC enable/pend/etc register accessors.\n+ */\n+ int i;\n+\n+ for (i = NVIC_FIRST_IRQ; i < ARRAY_SIZE(s->itns); i++) {\n+ s->itns[i] = true;\n+ }\n+ }\n }\n \n static void nvic_systick_trigger(void *opaque, int n, int level)\n", "prefixes": [ "07/19" ] }