Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/812948/?format=api
{ "id": 812948, "url": "http://patchwork.ozlabs.org/api/patches/812948/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/20170912160553.13422-3-npiggin@gmail.com/", "project": { "id": 44, "url": "http://patchwork.ozlabs.org/api/projects/44/?format=api", "name": "skiboot firmware development", "link_name": "skiboot", "list_id": "skiboot.lists.ozlabs.org", "list_email": "skiboot@lists.ozlabs.org", "web_url": "http://github.com/open-power/skiboot", "scm_url": "http://github.com/open-power/skiboot", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170912160553.13422-3-npiggin@gmail.com>", "list_archive_url": null, "date": "2017-09-12T16:05:53", "name": "[RFC,2/2] powerpc/powernv: implement NMI IPIs with OPAL_SIGNAL_SYSTEM_RESET", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "6514e20c093bf1dc27a1bca89a2a1abc1bf0f146", "submitter": { "id": 69518, "url": "http://patchwork.ozlabs.org/api/people/69518/?format=api", "name": "Nicholas Piggin", "email": "npiggin@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/20170912160553.13422-3-npiggin@gmail.com/mbox/", "series": [ { "id": 2735, "url": "http://patchwork.ozlabs.org/api/series/2735/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/list/?series=2735", "date": "2017-09-12T16:05:51", "name": "NMI IPI work in progress for Linux and OPAL", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2735/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812948/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812948/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs91h4BtRz9s7f\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 02:17:44 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xs91h2WWdzDrMP\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 02:17:44 +1000 (AEST)", "from mail-pg0-x244.google.com (mail-pg0-x244.google.com\n\t[IPv6:2607:f8b0:400e:c05::244])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xs8mS5NzMzDrW7;\n\tWed, 13 Sep 2017 02:06:16 +1000 (AEST)", "by mail-pg0-x244.google.com with SMTP id m30so1405223pgn.5;\n\tTue, 12 Sep 2017 09:06:16 -0700 (PDT)", "from roar.au.ibm.com (203-219-56-202.tpgi.com.au. [203.219.56.202])\n\tby smtp.gmail.com with ESMTPSA id\n\tq67sm21517424pfg.37.2017.09.12.09.06.10\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 12 Sep 2017 09:06:13 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"KVUnMlKk\"; dkim-atps=neutral", "lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"KVUnMlKk\"; dkim-atps=neutral", "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gmail.com\n\t(client-ip=2607:f8b0:400e:c05::244; helo=mail-pg0-x244.google.com;\n\tenvelope-from=npiggin@gmail.com; receiver=<UNKNOWN>)", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"KVUnMlKk\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=Ux+8A8EMdZGb5KMzXvnkXijFeQw0bS6DB8MraCtoNUs=;\n\tb=KVUnMlKkOAPpczG9P0QJVMl1Wj7U0aEJ++LPHeM9InJ7UeTchm83R0VR8vYA539JbU\n\thMlBgiDSK3rpR7yeg1+lHB+/HyY1taPjtsWP6nsLYz1u1Tz+oDzAKUBBwTfyL2ujkOuA\n\tzkGKsZ53pAoMnzP4KUBqTFDAOG+ZyNFdxaliOu5I3HbwDv0jTwLf3wCLT7qkWFuFAXj1\n\tqmbutjbycolmQ25kkIrQHDNaRrcXlHBxSpCIGf48UlFI6NyoGC/kv/dh8W//4Mi1NSRY\n\tLeGesYjhdzRPxNxn3QaRqISwW5usVjLg1hBVCvfN5bmoot0A/h7TJNUFo970bjjnzlpJ\n\tm1Jg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=Ux+8A8EMdZGb5KMzXvnkXijFeQw0bS6DB8MraCtoNUs=;\n\tb=fY44ipZZ4O+TFM1K1BshsBm1rYPvqybpEQ9+kEbGj3cd+Ywm6a3JjLpxY834R9yBGU\n\tBJAVjHP5rOI34riAey/AlsrRdUHddYbGlcoksXst+apEMhFjmg68KMSiKo5U2pmMn6Bt\n\t27GphUFhfwebDHXVgUS20VErVlyFbeF01Ys/XvdepDsLqDh80efEzSNzSJlq1+0h67dy\n\t8QiQkZ2ETZwTgvZ0+uIKNWADKiyO6vwFIERYifOVs9EKCRNTt8SIx30E+cqbNVNMy7Nd\n\tOQQbSArNaaLnOGC1dLKLrpZlWFhDuGuszyFx3HiynxFpQBDBpuip9TeoXS09tMbrP5Rh\n\tZfEw==", "X-Gm-Message-State": "AHPjjUiCXdYimqnKnGAjVvQCUlz+GsjM0sKuEA65QTc88rEdpoR6wWkt\n\tvG0VzmelfoHonUdC", "X-Google-Smtp-Source": "ADKCNb5b4hsTIWOqJWgvWX59NC6xaBs9Jm+JXKU38V72wAWprVmyR5kZ7uwmi2nTsPzoysvxbmVb5w==", "X-Received": "by 10.84.129.65 with SMTP id 59mr17476824plb.442.1505232374297; \n\tTue, 12 Sep 2017 09:06:14 -0700 (PDT)", "From": "Nicholas Piggin <npiggin@gmail.com>", "To": "linuxppc-dev@lists.ozlabs.org,\n\tskiboot@lists.ozlabs.org", "Date": "Wed, 13 Sep 2017 02:05:53 +1000", "Message-Id": "<20170912160553.13422-3-npiggin@gmail.com>", "X-Mailer": "git-send-email 2.13.3", "In-Reply-To": "<20170912160553.13422-1-npiggin@gmail.com>", "References": "<20170912160553.13422-1-npiggin@gmail.com>", "Subject": "[Skiboot] [RFC PATCH 2/2] powerpc/powernv: implement NMI IPIs with\n\tOPAL_SIGNAL_SYSTEM_RESET", "X-BeenThere": "skiboot@lists.ozlabs.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/skiboot/>", "List-Post": "<mailto:skiboot@lists.ozlabs.org>", "List-Help": "<mailto:skiboot-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Alistair Popple <alistair@popple.id.au>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Skiboot\"\n\t<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "There are two complications. The first is that sreset from stop states\ncome in with SRR1 set to do a powersave wakeup, with an sreset reason\nencoded.\n\nThe second is that threads on the same core can't be signalled directly\nso we must designate a bounce CPU to reflect the IPI back.\n---\n arch/powerpc/include/asm/opal-api.h | 1 +\n arch/powerpc/include/asm/opal.h | 2 +\n arch/powerpc/kernel/irq.c | 13 +++\n arch/powerpc/platforms/powernv/opal-wrappers.S | 1 +\n arch/powerpc/platforms/powernv/powernv.h | 1 +\n arch/powerpc/platforms/powernv/setup.c | 3 +\n arch/powerpc/platforms/powernv/smp.c | 111 +++++++++++++++++++++++++\n 7 files changed, 132 insertions(+)", "diff": "diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h\nindex 450a60b81d2a..bd9d1f2b3584 100644\n--- a/arch/powerpc/include/asm/opal-api.h\n+++ b/arch/powerpc/include/asm/opal-api.h\n@@ -188,6 +188,7 @@\n #define OPAL_XIVE_DUMP\t\t\t\t142\n #define OPAL_XIVE_RESERVED3\t\t\t143\n #define OPAL_XIVE_RESERVED4\t\t\t144\n+#define OPAL_SIGNAL_SYSTEM_RESET \t\t145\n #define OPAL_NPU_INIT_CONTEXT\t\t\t146\n #define OPAL_NPU_DESTROY_CONTEXT\t\t147\n #define OPAL_NPU_MAP_LPAR\t\t\t148\ndiff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h\nindex 726c23304a57..7d7613c49f2b 100644\n--- a/arch/powerpc/include/asm/opal.h\n+++ b/arch/powerpc/include/asm/opal.h\n@@ -281,6 +281,8 @@ int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);\n int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);\n int opal_sensor_group_clear(u32 group_hndl, int token);\n \n+int64_t opal_signal_system_reset(int32_t cpu);\n+\n /* Internal functions */\n extern int early_init_dt_scan_opal(unsigned long node, const char *uname,\n \t\t\t\t int depth, void *data);\ndiff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c\nindex 4e65bf82f5e0..3276e05cb53f 100644\n--- a/arch/powerpc/kernel/irq.c\n+++ b/arch/powerpc/kernel/irq.c\n@@ -407,10 +407,23 @@ static const u8 srr1_to_lazyirq[0x10] = {\n \tPACA_IRQ_HMI,\n \t0, 0, 0, 0, 0 };\n \n+static noinline void system_reset(void)\n+{\n+\tstruct pt_regs regs;\n+\tppc_save_regs(®s);\n+\n+\tget_paca()->in_nmi = 1;\n+\tsystem_reset_exception(®s);\n+\tget_paca()->in_nmi = 0;\n+}\n+\n void irq_set_pending_from_srr1(unsigned long srr1)\n {\n \tunsigned int idx = (srr1 & SRR1_WAKEMASK_P8) >> 18;\n \n+\tif (unlikely(idx == 2 || idx == 4))\n+\t\tsystem_reset();\n+\n \t/*\n \t * The 0 index (SRR1[42:45]=b0000) must always evaluate to 0,\n \t * so this can be called unconditionally with srr1 wake reason.\ndiff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S\nindex 8c1ede2d3f7e..37cd170201a2 100644\n--- a/arch/powerpc/platforms/powernv/opal-wrappers.S\n+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S\n@@ -307,6 +307,7 @@ OPAL_CALL(opal_xive_get_vp_info,\t\tOPAL_XIVE_GET_VP_INFO);\n OPAL_CALL(opal_xive_set_vp_info,\t\tOPAL_XIVE_SET_VP_INFO);\n OPAL_CALL(opal_xive_sync,\t\t\tOPAL_XIVE_SYNC);\n OPAL_CALL(opal_xive_dump,\t\t\tOPAL_XIVE_DUMP);\n+OPAL_CALL(opal_signal_system_reset,\t\tOPAL_SIGNAL_SYSTEM_RESET);\n OPAL_CALL(opal_npu_init_context,\t\tOPAL_NPU_INIT_CONTEXT);\n OPAL_CALL(opal_npu_destroy_context,\t\tOPAL_NPU_DESTROY_CONTEXT);\n OPAL_CALL(opal_npu_map_lpar,\t\t\tOPAL_NPU_MAP_LPAR);\ndiff --git a/arch/powerpc/platforms/powernv/powernv.h b/arch/powerpc/platforms/powernv/powernv.h\nindex a159d48573d7..49add2037e0d 100644\n--- a/arch/powerpc/platforms/powernv/powernv.h\n+++ b/arch/powerpc/platforms/powernv/powernv.h\n@@ -3,6 +3,7 @@\n \n #ifdef CONFIG_SMP\n extern void pnv_smp_init(void);\n+extern int pnv_system_reset_exception(struct pt_regs *regs);\n #else\n static inline void pnv_smp_init(void) { }\n #endif\ndiff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c\nindex 897aa1400eb8..4fdaa1d7c4cd 100644\n--- a/arch/powerpc/platforms/powernv/setup.c\n+++ b/arch/powerpc/platforms/powernv/setup.c\n@@ -282,6 +282,9 @@ static void __init pnv_setup_machdep_opal(void)\n \tppc_md.restart = pnv_restart;\n \tpm_power_off = pnv_power_off;\n \tppc_md.halt = pnv_halt;\n+#ifdef CONFIG_SMP\n+\tppc_md.system_reset_exception = pnv_system_reset_exception;\n+#endif\n \tppc_md.machine_check_exception = opal_machine_check;\n \tppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;\n \tppc_md.hmi_exception_early = opal_hmi_exception_early;\ndiff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c\nindex c17f81e433f7..45b1c191e3c8 100644\n--- a/arch/powerpc/platforms/powernv/smp.c\n+++ b/arch/powerpc/platforms/powernv/smp.c\n@@ -290,6 +290,112 @@ static void __init pnv_smp_probe(void)\n \t}\n }\n \n+static int nmi_ipi_bounce_cpu;\n+static int nmi_ipi_bounce_cpu_done;\n+static int nmi_ipi_bounce_target_core;\n+static int nmi_ipi_bounce_target_exclude;\n+\n+int pnv_system_reset_exception(struct pt_regs *regs)\n+{\n+\tsmp_mb();\n+\tif (nmi_ipi_bounce_cpu == smp_processor_id()) {\n+\t\tint64_t rc;\n+\t\tint c;\n+\n+\t\tnmi_ipi_bounce_cpu = -1;\n+\t\tsmp_mb();\n+\t\tfor_each_online_cpu(c) {\n+\t\t\tif (!cpumask_test_cpu(c, cpu_sibling_mask(nmi_ipi_bounce_target_core)))\n+\t\t\t\tcontinue;\n+\t\t\tif (c == nmi_ipi_bounce_target_exclude)\n+\t\t\t\tcontinue;\n+\t\t\trc = opal_signal_system_reset(get_hard_smp_processor_id(c));\n+\t\t\tif (rc != OPAL_SUCCESS) {\n+\t\t\t\tnmi_ipi_bounce_cpu_done = -1;\n+\t\t\t\treturn 1;\n+\t\t\t}\n+\t\t}\n+\t\tnmi_ipi_bounce_cpu_done = 1;\n+\t}\n+\n+\tif (smp_handle_nmi_ipi(regs))\n+\t\treturn 1;\n+\treturn 0;\n+}\n+\n+static int pnv_cause_nmi_ipi(int cpu)\n+{\n+\tint64_t rc;\n+\n+\tif (cpu >= 0) {\n+\t\trc = opal_signal_system_reset(get_hard_smp_processor_id(cpu));\n+\t\tif (rc == OPAL_SUCCESS)\n+\t\t\treturn 1;\n+\t\treturn 0;\n+\t} else {\n+\t\t/*\n+\t\t * Test bounce behavior with broadcast IPI.\n+\t\t */\n+\t\trc = OPAL_PARTIAL;\n+\t}\n+\tif (rc == OPAL_PARTIAL) {\n+\t\tint c;\n+\n+\t\t/*\n+\t\t * Some platforms can not send NMI to sibling threads in\n+\t\t * the same core. We can designate one inter-core target\n+\t\t * to bounce NMIs back to our sibling threads.\n+\t\t */\n+\n+\t\tif (cpu >= 0) {\n+\t\t\t/*\n+\t\t\t * Don't support bouncing unicast NMIs yet (because\n+\t\t\t * that would have to raise an NMI on an unrelated\n+\t\t\t * CPU. Revisit this if callers start using unicast.\n+\t\t\t */\n+\t\t\tprintk(\"CPU:%d pnv_cause_nmi_ipi can not bounce unicast IPIs!\\n\", smp_processor_id());\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\tnmi_ipi_bounce_cpu = -1;\n+\t\tnmi_ipi_bounce_cpu_done = 0;\n+\t\tnmi_ipi_bounce_target_core = -1;\n+\t\tnmi_ipi_bounce_target_exclude = -1;\n+\n+\t\tfor_each_online_cpu(c) {\n+\t\t\tif (cpumask_test_cpu(c, cpu_sibling_mask(smp_processor_id())))\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (nmi_ipi_bounce_cpu == -1) {\n+\t\t\t\tnmi_ipi_bounce_cpu = c;\n+\t\t\t\tnmi_ipi_bounce_target_core = smp_processor_id();\n+\t\t\t\tif (cpu == NMI_IPI_ALL_OTHERS)\n+\t\t\t\t\tnmi_ipi_bounce_target_exclude = smp_processor_id();\n+\t\t\t\tsmp_mb();\n+\t\t\t} else {\n+\t\t\t\trc = opal_signal_system_reset(get_hard_smp_processor_id(c));\n+\t\t\t\tif (rc != OPAL_SUCCESS)\n+\t\t\t\t\treturn 0;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (nmi_ipi_bounce_cpu == -1)\n+\t\t\treturn 0; /* could not find a bouncer */\n+\n+\t\trc = opal_signal_system_reset(get_hard_smp_processor_id(nmi_ipi_bounce_cpu));\n+\t\tif (rc != OPAL_SUCCESS)\n+\t\t\treturn 0;\n+\n+\t\twhile (!nmi_ipi_bounce_cpu_done)\n+\t\t\tcpu_relax();\n+\n+\t\tif (nmi_ipi_bounce_cpu_done == 1)\n+\t\t\treturn 1; /* bounce worked */\n+\t}\n+\n+\treturn 0;\n+}\n+\n static struct smp_ops_t pnv_smp_ops = {\n \t.message_pass\t= NULL, /* Use smp_muxed_ipi_message_pass */\n \t.cause_ipi\t= NULL,\t/* Filled at runtime by pnv_smp_probe() */\n@@ -308,6 +414,11 @@ static struct smp_ops_t pnv_smp_ops = {\n /* This is called very early during platform setup_arch */\n void __init pnv_smp_init(void)\n {\n+\tif (opal_check_token(OPAL_SIGNAL_SYSTEM_RESET)) {\n+\t\tprintk(\"OPAL_SIGNAL_SYSTEM_RESET available\\n\");\n+\t\tpnv_smp_ops.cause_nmi_ipi = pnv_cause_nmi_ipi;\n+\t} else\n+\t\tprintk(\"OPAL_SIGNAL_SYSTEM_RESET NOT available\\n\");\n \tsmp_ops = &pnv_smp_ops;\n \n #ifdef CONFIG_HOTPLUG_CPU\n", "prefixes": [ "RFC", "2/2" ] }