[{"id":1767874,"web_url":"http://patchwork.ozlabs.org/comment/1767874/","msgid":"<20170913231354.6b249fd0@roar.ozlabs.ibm.com>","list_archive_url":null,"date":"2017-09-13T13:13:54","subject":"Re: [Skiboot] [RFC PATCH 2/2] powerpc/powernv: implement NMI IPIs\n\twith OPAL_SIGNAL_SYSTEM_RESET","submitter":{"id":69518,"url":"http://patchwork.ozlabs.org/api/people/69518/","name":"Nicholas Piggin","email":"npiggin@gmail.com"},"content":"On Wed, 13 Sep 2017 02:05:53 +1000\nNicholas Piggin wrote:\n\n> There are two complications. The first is that sreset from stop states\n> come in with SRR1 set to do a powersave wakeup, with an sreset reason\n> encoded.\n> \n> The second is that threads on the same core can't be signalled directly\n> so we must designate a bounce CPU to reflect the IPI back.\n\nHere is an updated Linux patch for the latest OPAL patch. This has\na few assorted fixes as well to make it work nicely, I roll them into\none patch here to make it easy to apply for testing the OPAL patch.\n\nThanks,\nNick\n\n---\n arch/powerpc/include/asm/opal-api.h | 1 +\n arch/powerpc/include/asm/opal.h | 2 +\n arch/powerpc/kernel/irq.c | 18 ++++++\n arch/powerpc/kernel/watchdog.c | 30 +++++++--\n arch/powerpc/platforms/powernv/opal-wrappers.S | 1 +\n arch/powerpc/platforms/powernv/powernv.h | 1 +\n arch/powerpc/platforms/powernv/setup.c | 3 +\n arch/powerpc/platforms/powernv/smp.c | 89 ++++++++++++++++++++++++++\n arch/powerpc/xmon/xmon.c | 17 +++--\n 9 files changed, 151 insertions(+), 11 deletions(-)\n\ndiff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h\nindex 450a60b81d2a..e39f4236b413 100644\n--- a/arch/powerpc/include/asm/opal-api.h\n+++ b/arch/powerpc/include/asm/opal-api.h\n@@ -188,6 +188,7 @@\n #define OPAL_XIVE_DUMP\t\t\t\t142\n #define OPAL_XIVE_RESERVED3\t\t\t143\n #define OPAL_XIVE_RESERVED4\t\t\t144\n+#define OPAL_SIGNAL_SYSTEM_RESET 145\n #define OPAL_NPU_INIT_CONTEXT\t\t\t146\n #define OPAL_NPU_DESTROY_CONTEXT\t\t147\n #define OPAL_NPU_MAP_LPAR\t\t\t148\ndiff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h\nindex 726c23304a57..7d7613c49f2b 100644\n--- a/arch/powerpc/include/asm/opal.h\n+++ b/arch/powerpc/include/asm/opal.h\n@@ -281,6 +281,8 @@ int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);\n int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);\n int opal_sensor_group_clear(u32 group_hndl, int token);\n \n+int64_t opal_signal_system_reset(int32_t cpu);\n+\n /* Internal functions */\n extern int early_init_dt_scan_opal(unsigned long node, const char *uname,\n \t\t\t\t int depth, void *data);\ndiff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c\nindex 4e65bf82f5e0..5f2c0367bab2 100644\n--- a/arch/powerpc/kernel/irq.c\n+++ b/arch/powerpc/kernel/irq.c\n@@ -407,10 +407,28 @@ static const u8 srr1_to_lazyirq[0x10] = {\n \tPACA_IRQ_HMI,\n \t0, 0, 0, 0, 0 };\n \n+/*\n+ * System reset does not have to wait for Linux interrupts\n+ * to be re-enabled, so just replay it now.\n+ */\n+static noinline void replay_system_reset(void)\n+{\n+\tstruct pt_regs regs;\n+\n+\tppc_save_regs(®s);\n+\n+\tget_paca()->in_nmi = 1;\n+\tsystem_reset_exception(®s);\n+\tget_paca()->in_nmi = 0;\n+}\n+\n void irq_set_pending_from_srr1(unsigned long srr1)\n {\n \tunsigned int idx = (srr1 & SRR1_WAKEMASK_P8) >> 18;\n \n+\tif (unlikely(idx == 4))\n+\t\treplay_system_reset();\n+\n \t/*\n \t * The 0 index (SRR1[42:45]=b0000) must always evaluate to 0,\n \t * so this can be called unconditionally with srr1 wake reason.\ndiff --git a/arch/powerpc/kernel/watchdog.c b/arch/powerpc/kernel/watchdog.c\nindex 2f6eadd9408d..a6aa85b0cdeb 100644\n--- a/arch/powerpc/kernel/watchdog.c\n+++ b/arch/powerpc/kernel/watchdog.c\n@@ -61,6 +61,7 @@ static DEFINE_PER_CPU(u64, wd_timer_tb);\n */\n static unsigned long __wd_smp_lock;\n static cpumask_t wd_smp_cpus_pending;\n+static cpumask_t wd_smp_cpus_stuck_tmp;\n static cpumask_t wd_smp_cpus_stuck;\n static u64 wd_smp_last_reset_tb;\n \n@@ -97,8 +98,7 @@ static void wd_lockup_ipi(struct pt_regs *regs)\n \telse\n \t\tdump_stack();\n \n-\tif (hardlockup_panic)\n-\t\tnmi_panic(regs, \"Hard LOCKUP\");\n+\t/* Do not panic from here because that can recurse into NMI IPI layer */\n }\n \n static void set_cpumask_stuck(const struct cpumask *cpumask, u64 tb)\n@@ -136,16 +136,29 @@ static void watchdog_smp_panic(int cpu, u64 tb)\n \n \t/*\n \t * Try to trigger the stuck CPUs.\n+\t *\n+\t * There is a bit of a hack for OPAL here because it can not\n+\t * signal sibling threads. Don't try to signal those or mark\n+\t * them stuck, in the hope that another core will notice.\n \t */\n+\tcpumask_clear(&wd_smp_cpus_stuck_tmp);\n \tfor_each_cpu(c, &wd_smp_cpus_pending) {\n \t\tif (c == cpu)\n \t\t\tcontinue;\n-\t\tsmp_send_nmi_ipi(c, wd_lockup_ipi, 1000000);\n+\t\tif (firmware_has_feature(FW_FEATURE_OPAL)) {\n+\t\t\tif (cpumask_test_cpu(c, cpu_sibling_mask(cpu)))\n+\t\t\t\tcontinue;\n+\t\t}\n+\t\tcpumask_set_cpu(c, &wd_smp_cpus_stuck_tmp);\n+\t\tif (!sysctl_hardlockup_all_cpu_backtrace)\n+\t\t\tsmp_send_nmi_ipi(c, wd_lockup_ipi, 1000000);\n \t}\n-\tsmp_flush_nmi_ipi(1000000);\n \n \t/* Take the stuck CPUs out of the watch group */\n-\tset_cpumask_stuck(&wd_smp_cpus_pending, tb);\n+\tset_cpumask_stuck(&wd_smp_cpus_stuck_tmp, tb);\n+\n+\tif (!sysctl_hardlockup_all_cpu_backtrace)\n+\t\tsmp_flush_nmi_ipi(1000000);\n \n \twd_smp_unlock(&flags);\n \n@@ -275,9 +288,12 @@ void arch_touch_nmi_watchdog(void)\n {\n \tunsigned long ticks = tb_ticks_per_usec * wd_timer_period_ms * 1000;\n \tint cpu = smp_processor_id();\n+\tu64 tb = get_tb();\n \n-\tif (get_tb() - per_cpu(wd_timer_tb, cpu) >= ticks)\n-\t\twatchdog_timer_interrupt(cpu);\n+\tif (tb - per_cpu(wd_timer_tb, cpu) >= ticks) {\n+\t\tper_cpu(wd_timer_tb, cpu) = tb;\n+\t\twd_smp_clear_cpu_pending(cpu, tb);\n+\t}\n }\n EXPORT_SYMBOL(arch_touch_nmi_watchdog);\n \ndiff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S\nindex 8c1ede2d3f7e..37cd170201a2 100644\n--- a/arch/powerpc/platforms/powernv/opal-wrappers.S\n+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S\n@@ -307,6 +307,7 @@ OPAL_CALL(opal_xive_get_vp_info,\t\tOPAL_XIVE_GET_VP_INFO);\n OPAL_CALL(opal_xive_set_vp_info,\t\tOPAL_XIVE_SET_VP_INFO);\n OPAL_CALL(opal_xive_sync,\t\t\tOPAL_XIVE_SYNC);\n OPAL_CALL(opal_xive_dump,\t\t\tOPAL_XIVE_DUMP);\n+OPAL_CALL(opal_signal_system_reset,\t\tOPAL_SIGNAL_SYSTEM_RESET);\n OPAL_CALL(opal_npu_init_context,\t\tOPAL_NPU_INIT_CONTEXT);\n OPAL_CALL(opal_npu_destroy_context,\t\tOPAL_NPU_DESTROY_CONTEXT);\n OPAL_CALL(opal_npu_map_lpar,\t\t\tOPAL_NPU_MAP_LPAR);\ndiff --git a/arch/powerpc/platforms/powernv/powernv.h b/arch/powerpc/platforms/powernv/powernv.h\nindex a159d48573d7..49add2037e0d 100644\n--- a/arch/powerpc/platforms/powernv/powernv.h\n+++ b/arch/powerpc/platforms/powernv/powernv.h\n@@ -3,6 +3,7 @@\n \n #ifdef CONFIG_SMP\n extern void pnv_smp_init(void);\n+extern int pnv_system_reset_exception(struct pt_regs *regs);\n #else\n static inline void pnv_smp_init(void) { }\n #endif\ndiff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c\nindex 897aa1400eb8..4fdaa1d7c4cd 100644\n--- a/arch/powerpc/platforms/powernv/setup.c\n+++ b/arch/powerpc/platforms/powernv/setup.c\n@@ -282,6 +282,9 @@ static void __init pnv_setup_machdep_opal(void)\n \tppc_md.restart = pnv_restart;\n \tpm_power_off = pnv_power_off;\n \tppc_md.halt = pnv_halt;\n+#ifdef CONFIG_SMP\n+\tppc_md.system_reset_exception = pnv_system_reset_exception;\n+#endif\n \tppc_md.machine_check_exception = opal_machine_check;\n \tppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;\n \tppc_md.hmi_exception_early = opal_hmi_exception_early;\ndiff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c\nindex c17f81e433f7..9da97962c93a 100644\n--- a/arch/powerpc/platforms/powernv/smp.c\n+++ b/arch/powerpc/platforms/powernv/smp.c\n@@ -290,6 +290,93 @@ static void __init pnv_smp_probe(void)\n \t}\n }\n \n+static int nmi_ipi_bounce_cpu;\n+static int nmi_ipi_bounce_target_core;\n+static int nmi_ipi_bounce_target_exclude;\n+\n+int pnv_system_reset_exception(struct pt_regs *regs)\n+{\n+\tif (nmi_ipi_bounce_cpu == smp_processor_id()) {\n+\t\tint c;\n+\t\tnmi_ipi_bounce_cpu = -1;\n+\t\tfor_each_online_cpu(c) {\n+\t\t\tif (!cpumask_test_cpu(c, cpu_sibling_mask(\n+\t\t\t\t\t\tnmi_ipi_bounce_target_core)))\n+\t\t\t\tcontinue;\n+\t\t\tif (c == nmi_ipi_bounce_target_exclude)\n+\t\t\t\tcontinue;\n+\t\t\topal_signal_system_reset(\n+\t\t\t\t\tget_hard_smp_processor_id(c));\n+\t\t\t/* can't do much with failure here */\n+\t\t}\n+\t}\n+\n+\tif (smp_handle_nmi_ipi(regs))\n+\t\treturn 1;\n+\treturn 0;\n+}\n+\n+static int pnv_cause_nmi_ipi(int cpu)\n+{\n+\tint64_t rc;\n+\n+\tif (cpu >= 0) {\n+\t\trc = opal_signal_system_reset(get_hard_smp_processor_id(cpu));\n+\t\tif (rc == OPAL_SUCCESS)\n+\t\t\treturn 1;\n+\t\treturn 0;\n+\t} else {\n+\t\tint c;\n+\n+\t\t/*\n+\t\t * Some platforms can not send NMI to sibling threads in\n+\t\t * the same core. We can designate one inter-core target\n+\t\t * to bounce NMIs back to our sibling threads.\n+\t\t */\n+\n+\t\tif (cpu >= 0) {\n+\t\t\t/*\n+\t\t\t * Don't support bouncing unicast NMIs yet (because\n+\t\t\t * that would have to raise an NMI on an unrelated\n+\t\t\t * CPU. Revisit this if callers start using unicast.\n+\t\t\t */\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\tnmi_ipi_bounce_cpu = -1;\n+\t\tnmi_ipi_bounce_target_core = -1;\n+\t\tnmi_ipi_bounce_target_exclude = -1;\n+\n+\t\tfor_each_online_cpu(c) {\n+\t\t\tif (cpumask_test_cpu(c, cpu_sibling_mask(smp_processor_id())))\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (nmi_ipi_bounce_cpu == -1) {\n+\t\t\t\tnmi_ipi_bounce_cpu = c;\n+\t\t\t\tnmi_ipi_bounce_target_core = smp_processor_id();\n+\t\t\t\tif (cpu == NMI_IPI_ALL_OTHERS)\n+\t\t\t\t\tnmi_ipi_bounce_target_exclude = smp_processor_id();\n+\t\t\t\tsmp_mb();\n+\t\t\t} else {\n+\t\t\t\trc = opal_signal_system_reset(\n+\t\t\t\t\t\tget_hard_smp_processor_id(c));\n+\t\t\t\tif (rc != OPAL_SUCCESS)\n+\t\t\t\t\treturn 0;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (nmi_ipi_bounce_cpu == -1)\n+\t\t\treturn 0; /* could not find a bouncer */\n+\t\trc = opal_signal_system_reset(\n+\t\t\t\tget_hard_smp_processor_id(nmi_ipi_bounce_cpu));\n+\t\tif (rc != OPAL_SUCCESS)\n+\t\t\treturn 0;\n+\t\treturn 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n static struct smp_ops_t pnv_smp_ops = {\n \t.message_pass\t= NULL, /* Use smp_muxed_ipi_message_pass */\n \t.cause_ipi\t= NULL,\t/* Filled at runtime by pnv_smp_probe() */\n@@ -308,6 +395,8 @@ static struct smp_ops_t pnv_smp_ops = {\n /* This is called very early during platform setup_arch */\n void __init pnv_smp_init(void)\n {\n+\tif (opal_check_token(OPAL_SIGNAL_SYSTEM_RESET))\n+\t\tpnv_smp_ops.cause_nmi_ipi = pnv_cause_nmi_ipi;\n \tsmp_ops = &pnv_smp_ops;\n \n #ifdef CONFIG_HOTPLUG_CPU\ndiff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c\nindex 33351c6704b1..d9a12102b111 100644\n--- a/arch/powerpc/xmon/xmon.c\n+++ b/arch/powerpc/xmon/xmon.c\n@@ -530,14 +530,19 @@ static int xmon_core(struct pt_regs *regs, int fromipi)\n \n waiting:\n \tsecondary = 1;\n+\tspin_begin();\n \twhile (secondary && !xmon_gate) {\n \t\tif (in_xmon == 0) {\n-\t\t\tif (fromipi)\n+\t\t\tif (fromipi) {\n+\t\t\t\tspin_end();\n \t\t\t\tgoto leave;\n+\t\t\t}\n \t\t\tsecondary = test_and_set_bit(0, &in_xmon);\n \t\t}\n-\t\tbarrier();\n+\t\tspin_cpu_relax();\n+\t\ttouch_nmi_watchdog();\n \t}\n+\tspin_end();\n \n \tif (!secondary && !xmon_gate) {\n \t\t/* we are the first cpu to come in */\n@@ -568,21 +573,25 @@ static int xmon_core(struct pt_regs *regs, int fromipi)\n \t\tmb();\n \t\txmon_gate = 1;\n \t\tbarrier();\n+\t\ttouch_nmi_watchdog();\n \t}\n \n cmdloop:\n \twhile (in_xmon) {\n \t\tif (secondary) {\n+\t\t\tspin_begin();\n \t\t\tif (cpu == xmon_owner) {\n \t\t\t\tif (!test_and_set_bit(0, &xmon_taken)) {\n \t\t\t\t\tsecondary = 0;\n+\t\t\t\t\tspin_end();\n \t\t\t\t\tcontinue;\n \t\t\t\t}\n \t\t\t\t/* missed it */\n \t\t\t\twhile (cpu == xmon_owner)\n-\t\t\t\t\tbarrier();\n+\t\t\t\t\tspin_cpu_relax();\n \t\t\t}\n-\t\t\tbarrier();\n+\t\t\tspin_cpu_relax();\n+\t\t\ttouch_nmi_watchdog();\n \t\t} else {\n \t\t\tcmd = cmds(regs);\n \t\t\tif (cmd != 0) {","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xshyP6L7Nz9s4s\n\tfor ;\n\tWed, 13 Sep 2017 23:16:45 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xshyP51YPzDrKf\n\tfor ;\n\tWed, 13 Sep 2017 23:16:45 +1000 (AEST)","from mail-pg0-x243.google.com (mail-pg0-x243.google.com\n\t[IPv6:2607:f8b0:400e:c05::243])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xshvf37GrzDrJq;\n\tWed, 13 Sep 2017 23:14:22 +1000 (AEST)","by mail-pg0-x243.google.com with SMTP id v82so87002pgb.1;\n\tWed, 13 Sep 2017 06:14:22 -0700 (PDT)","from roar.ozlabs.ibm.com (203-219-56-202.tpgi.com.au.\n\t[203.219.56.202]) by smtp.gmail.com with ESMTPSA id\n\to186sm13949796pfg.144.2017.09.13.06.14.15\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 13 Sep 2017 06:14:18 -0700 (PDT)"],"Authentication-Results":["ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"lToOERQC\"; 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x86_64-pc-linux-gnu)","MIME-Version":"1.0","Subject":"Re: [Skiboot] [RFC PATCH 2/2] powerpc/powernv: implement NMI IPIs\n\twith OPAL_SIGNAL_SYSTEM_RESET","X-BeenThere":"skiboot@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Mailing list for skiboot development ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Popple ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"}},{"id":1768303,"web_url":"http://patchwork.ozlabs.org/comment/1768303/","msgid":"<1505355889.12628.177.camel@kernel.crashing.org>","list_archive_url":null,"date":"2017-09-14T02:24:49","subject":"Re: [Skiboot] [RFC PATCH 2/2] powerpc/powernv: implement NMI IPIs\n\twith OPAL_SIGNAL_SYSTEM_RESET","submitter":{"id":38,"url":"http://patchwork.ozlabs.org/api/people/38/","name":"Benjamin Herrenschmidt","email":"benh@kernel.crashing.org"},"content":"On Wed, 2017-09-13 at 23:13 +1000, Nicholas Piggin wrote:\n> On Wed, 13 Sep 2017 02:05:53 +1000\n> Nicholas Piggin wrote:\n> \n> > There are two complications. The first is that sreset from stop states\n> > come in with SRR1 set to do a powersave wakeup, with an sreset reason\n> > encoded.\n> > \n> > The second is that threads on the same core can't be signalled directly\n> > so we must designate a bounce CPU to reflect the IPI back.\n> \n> Here is an updated Linux patch for the latest OPAL patch. This has\n> a few assorted fixes as well to make it work nicely, I roll them into\n> one patch here to make it easy to apply for testing the OPAL patch.\n\nWhy can't you sreset threads of the same core on P9 ?\n\nCheers,\nBen.","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xt2Tg257xz9t2V\n\tfor ;\n\tThu, 14 Sep 2017 12:26:31 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xt2Tg0yYwzDr5G\n\tfor ;\n\tThu, 14 Sep 2017 12:26:31 +1000 (AEST)","from gate.crashing.org (gate.crashing.org [63.228.1.57])\n\t(using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xt2Ry4pW9zDqYR;\n\tThu, 14 Sep 2017 12:25:02 +1000 (AEST)","from localhost (localhost.localdomain [127.0.0.1])\n\tby gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8E2Oocn031477;\n\tWed, 13 Sep 2017 21:24:51 -0500"],"Authentication-Results":"ozlabs.org; spf=permerror (mailfrom)\n\tsmtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57;\n\thelo=gate.crashing.org; envelope-from=benh@kernel.crashing.org;\n\treceiver=)","Message-ID":"<1505355889.12628.177.camel@kernel.crashing.org>","From":"Benjamin Herrenschmidt ","To":"Nicholas Piggin , linuxppc-dev@lists.ozlabs.org,\n\tskiboot@lists.ozlabs.org","Date":"Thu, 14 Sep 2017 12:24:49 +1000","In-Reply-To":"<20170913231354.6b249fd0@roar.ozlabs.ibm.com>","References":"<20170912160553.13422-1-npiggin@gmail.com>\n\t<20170912160553.13422-3-npiggin@gmail.com>\n\t<20170913231354.6b249fd0@roar.ozlabs.ibm.com>","X-Mailer":"Evolution 3.24.5 (3.24.5-1.fc26) ","Mime-Version":"1.0","Subject":"Re: [Skiboot] [RFC PATCH 2/2] powerpc/powernv: implement NMI IPIs\n\twith OPAL_SIGNAL_SYSTEM_RESET","X-BeenThere":"skiboot@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Mailing list for skiboot development ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Popple ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"}},{"id":1768357,"web_url":"http://patchwork.ozlabs.org/comment/1768357/","msgid":"<20170914163228.0510251a@roar.ozlabs.ibm.com>","list_archive_url":null,"date":"2017-09-14T06:32:28","subject":"Re: [Skiboot] [RFC PATCH 2/2] powerpc/powernv: implement NMI IPIs\n\twith OPAL_SIGNAL_SYSTEM_RESET","submitter":{"id":69518,"url":"http://patchwork.ozlabs.org/api/people/69518/","name":"Nicholas Piggin","email":"npiggin@gmail.com"},"content":"On Thu, 14 Sep 2017 12:24:49 +1000\nBenjamin Herrenschmidt wrote:\n\n> On Wed, 2017-09-13 at 23:13 +1000, Nicholas Piggin wrote:\n> > On Wed, 13 Sep 2017 02:05:53 +1000\n> > Nicholas Piggin wrote:\n> > \n> > > There are two complications. The first is that sreset from stop states\n> > > come in with SRR1 set to do a powersave wakeup, with an sreset reason\n> > > encoded.\n> > > \n> > > The second is that threads on the same core can't be signalled directly\n> > > so we must designate a bounce CPU to reflect the IPI back. \n> > \n> > Here is an updated Linux patch for the latest OPAL patch. This has\n> > a few assorted fixes as well to make it work nicely, I roll them into\n> > one patch here to make it easy to apply for testing the OPAL patch. \n> \n> Why can't you sreset threads of the same core on P9 ?\n\nIt looks like we can, I think I had some other bugs still not ironed\nout when I previously tested it.\n\nThat simplifies things a lot on the Linux side. It may be that the\nbounce is still required if we implement it on POWER8 using ramming,\nbut I'll get the POWER9 code in first.\n\nThanks,\nNick","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xt80S59Dzz9t1t\n\tfor ;\n\tThu, 14 Sep 2017 16:35:04 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xt80S3pGSzDrW4\n\tfor ;\n\tThu, 14 Sep 2017 16:35:04 +1000 (AEST)","from mail-pg0-x243.google.com (mail-pg0-x243.google.com\n\t[IPv6:2607:f8b0:400e:c05::243])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xt7xv4RDjzDrFt;\n\tThu, 14 Sep 2017 16:32:51 +1000 (AEST)","by mail-pg0-x243.google.com with SMTP id v82so1244951pgb.1;\n\tWed, 13 Sep 2017 23:32:51 -0700 (PDT)","from roar.ozlabs.ibm.com (203-219-56-202.tpgi.com.au.\n\t[203.219.56.202]) by smtp.gmail.com with ESMTPSA id\n\te16sm27326858pfb.170.2017.09.13.23.32.45\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 13 Sep 2017 23:32:48 -0700 (PDT)"],"Authentication-Results":["ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"tAZiWAfK\"; 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x86_64-pc-linux-gnu)","MIME-Version":"1.0","Subject":"Re: [Skiboot] [RFC PATCH 2/2] powerpc/powernv: implement NMI IPIs\n\twith OPAL_SIGNAL_SYSTEM_RESET","X-BeenThere":"skiboot@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Mailing list for skiboot development ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"skiboot@lists.ozlabs.org, linuxppc-dev@lists.ozlabs.org,\n\tAlistair Popple ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"}},{"id":1768364,"web_url":"http://patchwork.ozlabs.org/comment/1768364/","msgid":"<2623107.WiHgLWVaNd@new-mexico>","list_archive_url":null,"date":"2017-09-14T06:43:22","subject":"Re: [Skiboot] [RFC PATCH 2/2] powerpc/powernv: implement NMI IPIs\n\twith OPAL_SIGNAL_SYSTEM_RESET","submitter":{"id":24781,"url":"http://patchwork.ozlabs.org/api/people/24781/","name":"Alistair Popple","email":"alistair@popple.id.au"},"content":"On Thu, 14 Sep 2017 04:32:28 PM Nicholas Piggin wrote:\n> On Thu, 14 Sep 2017 12:24:49 +1000\n> Benjamin Herrenschmidt wrote:\n> \n> > On Wed, 2017-09-13 at 23:13 +1000, Nicholas Piggin wrote:\n> > > On Wed, 13 Sep 2017 02:05:53 +1000\n> > > Nicholas Piggin wrote:\n> > > \n> > > > There are two complications. The first is that sreset from stop states\n> > > > come in with SRR1 set to do a powersave wakeup, with an sreset reason\n> > > > encoded.\n> > > > \n> > > > The second is that threads on the same core can't be signalled directly\n> > > > so we must designate a bounce CPU to reflect the IPI back. \n> > > \n> > > Here is an updated Linux patch for the latest OPAL patch. This has\n> > > a few assorted fixes as well to make it work nicely, I roll them into\n> > > one patch here to make it easy to apply for testing the OPAL patch. \n> > \n> > Why can't you sreset threads of the same core on P9 ?\n> \n> It looks like we can, I think I had some other bugs still not ironed\n> out when I previously tested it.\n> \n> That simplifies things a lot on the Linux side. It may be that the\n> bounce is still required if we implement it on POWER8 using ramming,\n> but I'll get the POWER9 code in first.\n\nRight, the bouncing is still required on P8 because we need to ram instructions\nand you can only ram instructions if all threads on a core are quiesced.\n\n- Alistair\n\n>\n> Thanks,\n> Nick","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xt8Cm1hzyz9t1t\n\tfor ;\n\tThu, 14 Sep 2017 16:44:52 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xt8Cm0rmTzDrXP\n\tfor ;\n\tThu, 14 Sep 2017 16:44:52 +1000 (AEST)","from ipmail02.adl2.internode.on.net (ipmail02.adl2.internode.on.net\n\t[150.101.137.139])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xt8B43SwszDrJ7;\n\tThu, 14 Sep 2017 16:43:24 +1000 (AEST)","from static-82-10.transact.net.au (HELO new-mexico.localnet)\n\t([122.99.82.10]) by ipmail02.adl2.internode.on.net with ESMTP;\n\t14 Sep 2017 16:13:23 +0930"],"Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=popple.id.au\n\t(client-ip=150.101.137.139; helo=ipmail02.adl2.internode.on.net;\n\tenvelope-from=alistair@popple.id.au; receiver=)","X-IronPort-Anti-Spam-Filtered":"true","X-IronPort-Anti-Spam-Result":"A2BeBABYJLpZ/wpSY3pcHQEFAQsBhSwnhVaJNZEniDuJBoZ4hUYChR0UAQIBAQEBAQEBayiFGAEBAQECATo/EAsOCgkVEA8BETYGE4oaAw0Hr0aHOg2DbgEBAQcCASWDK4U1gyiCWIgTBaA9PI9bhWmSBEiMD4oSNiGBDRwWGAkIGBmGGIFgLjaJAgEBAQ","From":"Alistair Popple ","To":"Nicholas Piggin ","Date":"Thu, 14 Sep 2017 16:43:22 +1000","Message-ID":"<2623107.WiHgLWVaNd@new-mexico>","User-Agent":"KMail/4.14.1 (Linux/4.9.0-0.bpo.3-amd64; KDE/4.14.2; x86_64; ; )","In-Reply-To":"<20170914163228.0510251a@roar.ozlabs.ibm.com>","References":"<20170912160553.13422-1-npiggin@gmail.com>\n\t<1505355889.12628.177.camel@kernel.crashing.org>\n\t<20170914163228.0510251a@roar.ozlabs.ibm.com>","MIME-Version":"1.0","Subject":"Re: [Skiboot] [RFC PATCH 2/2] powerpc/powernv: implement NMI IPIs\n\twith OPAL_SIGNAL_SYSTEM_RESET","X-BeenThere":"skiboot@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Mailing list for skiboot development ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linuxppc-dev@lists.ozlabs.org, skiboot@lists.ozlabs.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"}},{"id":1768530,"web_url":"http://patchwork.ozlabs.org/comment/1768530/","msgid":"<20170914212603.356c66b1@roar.ozlabs.ibm.com>","list_archive_url":null,"date":"2017-09-14T11:26:03","subject":"Re: [Skiboot] [RFC PATCH 2/2] powerpc/powernv: implement NMI IPIs\n\twith OPAL_SIGNAL_SYSTEM_RESET","submitter":{"id":69518,"url":"http://patchwork.ozlabs.org/api/people/69518/","name":"Nicholas Piggin","email":"npiggin@gmail.com"},"content":"On Wed, 13 Sep 2017 02:05:53 +1000\nNicholas Piggin wrote:\n\n> There are two complications. The first is that sreset from stop states\n> come in with SRR1 set to do a powersave wakeup, with an sreset reason\n> encoded.\n> \n> The second is that threads on the same core can't be signalled directly\n> so we must designate a bounce CPU to reflect the IPI back.\n\nThis is a revised patch with only DD2 enablement. DD2 allows threads on\nthe same core to be IPIed. It's much simpler, and most of the code is\nfixing the watchdog and preventing it from triggering from xmon (which\nwill be split into other patches of course).\n\nIt's probably a better starting point to get this working and merged\nfirst, then revisiting bouncing.\n\n---\n arch/powerpc/include/asm/opal-api.h | 1 +\n arch/powerpc/include/asm/opal.h | 2 ++\n arch/powerpc/kernel/irq.c | 20 ++++++++++++++++++\n arch/powerpc/kernel/watchdog.c | 29 +++++++++++++++-----------\n arch/powerpc/platforms/powernv/opal-wrappers.S | 1 +\n arch/powerpc/platforms/powernv/powernv.h | 1 +\n arch/powerpc/platforms/powernv/setup.c | 3 +++\n arch/powerpc/platforms/powernv/smp.c | 24 +++++++++++++++++++++\n arch/powerpc/xmon/xmon.c | 17 +++++++++++----\n 9 files changed, 82 insertions(+), 16 deletions(-)\n\ndiff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h\nindex 450a60b81d2a..9d191ebea706 100644\n--- a/arch/powerpc/include/asm/opal-api.h\n+++ b/arch/powerpc/include/asm/opal-api.h\n@@ -188,6 +188,7 @@\n #define OPAL_XIVE_DUMP\t\t\t\t142\n #define OPAL_XIVE_RESERVED3\t\t\t143\n #define OPAL_XIVE_RESERVED4\t\t\t144\n+#define OPAL_SIGNAL_SYSTEM_RESET\t\t145\n #define OPAL_NPU_INIT_CONTEXT\t\t\t146\n #define OPAL_NPU_DESTROY_CONTEXT\t\t147\n #define OPAL_NPU_MAP_LPAR\t\t\t148\ndiff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h\nindex 726c23304a57..7d7613c49f2b 100644\n--- a/arch/powerpc/include/asm/opal.h\n+++ b/arch/powerpc/include/asm/opal.h\n@@ -281,6 +281,8 @@ int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);\n int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);\n int opal_sensor_group_clear(u32 group_hndl, int token);\n \n+int64_t opal_signal_system_reset(int32_t cpu);\n+\n /* Internal functions */\n extern int early_init_dt_scan_opal(unsigned long node, const char *uname,\n \t\t\t\t int depth, void *data);\ndiff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c\nindex 4e65bf82f5e0..8ffebb9437e5 100644\n--- a/arch/powerpc/kernel/irq.c\n+++ b/arch/powerpc/kernel/irq.c\n@@ -407,11 +407,31 @@ static const u8 srr1_to_lazyirq[0x10] = {\n \tPACA_IRQ_HMI,\n \t0, 0, 0, 0, 0 };\n \n+static noinline void replay_system_reset(void)\n+{\n+\tstruct pt_regs regs;\n+\n+\tppc_save_regs(®s);\n+\n+\tget_paca()->in_nmi = 1;\n+\tsystem_reset_exception(®s);\n+\tget_paca()->in_nmi = 0;\n+}\n+\n void irq_set_pending_from_srr1(unsigned long srr1)\n {\n \tunsigned int idx = (srr1 & SRR1_WAKEMASK_P8) >> 18;\n \n \t/*\n+\t * 0100b SRR1 reason is system reset. Take it now,\n+\t * which is immediately after registers are restored\n+\t * from idle. It's an NMI, so interrupts needn't be\n+\t * re-enabled.\n+\t */\n+\tif (unlikely(idx == 4))\n+\t\treplay_system_reset();\n+\n+\t/*\n \t * The 0 index (SRR1[42:45]=b0000) must always evaluate to 0,\n \t * so this can be called unconditionally with srr1 wake reason.\n \t */\ndiff --git a/arch/powerpc/kernel/watchdog.c b/arch/powerpc/kernel/watchdog.c\nindex 2f6eadd9408d..1fb9379dc683 100644\n--- a/arch/powerpc/kernel/watchdog.c\n+++ b/arch/powerpc/kernel/watchdog.c\n@@ -97,8 +97,7 @@ static void wd_lockup_ipi(struct pt_regs *regs)\n \telse\n \t\tdump_stack();\n \n-\tif (hardlockup_panic)\n-\t\tnmi_panic(regs, \"Hard LOCKUP\");\n+\t/* Do not panic from here because that can recurse into NMI IPI layer */\n }\n \n static void set_cpumask_stuck(const struct cpumask *cpumask, u64 tb)\n@@ -134,15 +133,18 @@ static void watchdog_smp_panic(int cpu, u64 tb)\n \tpr_emerg(\"Watchdog CPU:%d detected Hard LOCKUP other CPUS:%*pbl\\n\",\n \t\t\tcpu, cpumask_pr_args(&wd_smp_cpus_pending));\n \n-\t/*\n-\t * Try to trigger the stuck CPUs.\n-\t */\n-\tfor_each_cpu(c, &wd_smp_cpus_pending) {\n-\t\tif (c == cpu)\n-\t\t\tcontinue;\n-\t\tsmp_send_nmi_ipi(c, wd_lockup_ipi, 1000000);\n+\tif (!sysctl_hardlockup_all_cpu_backtrace) {\n+\t\t/*\n+\t\t * Try to trigger the stuck CPUs, unless we are going to\n+\t\t * get a backtrace on all of them anyway.\n+\t\t */\n+\t\tfor_each_cpu(c, &wd_smp_cpus_pending) {\n+\t\t\tif (c == cpu)\n+\t\t\t\tcontinue;\n+\t\t\tsmp_send_nmi_ipi(c, wd_lockup_ipi, 1000000);\n+\t\t}\n+\t\tsmp_flush_nmi_ipi(1000000);\n \t}\n-\tsmp_flush_nmi_ipi(1000000);\n \n \t/* Take the stuck CPUs out of the watch group */\n \tset_cpumask_stuck(&wd_smp_cpus_pending, tb);\n@@ -275,9 +277,12 @@ void arch_touch_nmi_watchdog(void)\n {\n \tunsigned long ticks = tb_ticks_per_usec * wd_timer_period_ms * 1000;\n \tint cpu = smp_processor_id();\n+\tu64 tb = get_tb();\n \n-\tif (get_tb() - per_cpu(wd_timer_tb, cpu) >= ticks)\n-\t\twatchdog_timer_interrupt(cpu);\n+\tif (tb - per_cpu(wd_timer_tb, cpu) >= ticks) {\n+\t\tper_cpu(wd_timer_tb, cpu) = tb;\n+\t\twd_smp_clear_cpu_pending(cpu, tb);\n+\t}\n }\n EXPORT_SYMBOL(arch_touch_nmi_watchdog);\n \ndiff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S\nindex 8c1ede2d3f7e..37cd170201a2 100644\n--- a/arch/powerpc/platforms/powernv/opal-wrappers.S\n+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S\n@@ -307,6 +307,7 @@ OPAL_CALL(opal_xive_get_vp_info,\t\tOPAL_XIVE_GET_VP_INFO);\n OPAL_CALL(opal_xive_set_vp_info,\t\tOPAL_XIVE_SET_VP_INFO);\n OPAL_CALL(opal_xive_sync,\t\t\tOPAL_XIVE_SYNC);\n OPAL_CALL(opal_xive_dump,\t\t\tOPAL_XIVE_DUMP);\n+OPAL_CALL(opal_signal_system_reset,\t\tOPAL_SIGNAL_SYSTEM_RESET);\n OPAL_CALL(opal_npu_init_context,\t\tOPAL_NPU_INIT_CONTEXT);\n OPAL_CALL(opal_npu_destroy_context,\t\tOPAL_NPU_DESTROY_CONTEXT);\n OPAL_CALL(opal_npu_map_lpar,\t\t\tOPAL_NPU_MAP_LPAR);\ndiff --git a/arch/powerpc/platforms/powernv/powernv.h b/arch/powerpc/platforms/powernv/powernv.h\nindex a159d48573d7..49add2037e0d 100644\n--- a/arch/powerpc/platforms/powernv/powernv.h\n+++ b/arch/powerpc/platforms/powernv/powernv.h\n@@ -3,6 +3,7 @@\n \n #ifdef CONFIG_SMP\n extern void pnv_smp_init(void);\n+extern int pnv_system_reset_exception(struct pt_regs *regs);\n #else\n static inline void pnv_smp_init(void) { }\n #endif\ndiff --git a/arch/powerpc/platforms/powernv/setup.c b/arch/powerpc/platforms/powernv/setup.c\nindex 897aa1400eb8..4fdaa1d7c4cd 100644\n--- a/arch/powerpc/platforms/powernv/setup.c\n+++ b/arch/powerpc/platforms/powernv/setup.c\n@@ -282,6 +282,9 @@ static void __init pnv_setup_machdep_opal(void)\n \tppc_md.restart = pnv_restart;\n \tpm_power_off = pnv_power_off;\n \tppc_md.halt = pnv_halt;\n+#ifdef CONFIG_SMP\n+\tppc_md.system_reset_exception = pnv_system_reset_exception;\n+#endif\n \tppc_md.machine_check_exception = opal_machine_check;\n \tppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;\n \tppc_md.hmi_exception_early = opal_hmi_exception_early;\ndiff --git a/arch/powerpc/platforms/powernv/smp.c b/arch/powerpc/platforms/powernv/smp.c\nindex c17f81e433f7..83343832e07e 100644\n--- a/arch/powerpc/platforms/powernv/smp.c\n+++ b/arch/powerpc/platforms/powernv/smp.c\n@@ -290,6 +290,28 @@ static void __init pnv_smp_probe(void)\n \t}\n }\n \n+int pnv_system_reset_exception(struct pt_regs *regs)\n+{\n+\tif (smp_handle_nmi_ipi(regs))\n+\t\treturn 1;\n+\treturn 0;\n+}\n+\n+static int pnv_cause_nmi_ipi(int cpu)\n+{\n+\tint64_t rc;\n+\n+\trc = opal_signal_system_reset(cpu);\n+\tif (rc == OPAL_SUCCESS)\n+\t\treturn 1;\n+\n+\t/*\n+\t * Don't cope with OPAL_PARTIAL yet (just punt to regular IPI)\n+\t */\n+\n+\treturn 0;\n+}\n+\n static struct smp_ops_t pnv_smp_ops = {\n \t.message_pass\t= NULL, /* Use smp_muxed_ipi_message_pass */\n \t.cause_ipi\t= NULL,\t/* Filled at runtime by pnv_smp_probe() */\n@@ -308,6 +330,8 @@ static struct smp_ops_t pnv_smp_ops = {\n /* This is called very early during platform setup_arch */\n void __init pnv_smp_init(void)\n {\n+\tif (opal_check_token(OPAL_SIGNAL_SYSTEM_RESET))\n+\t\tpnv_smp_ops.cause_nmi_ipi = pnv_cause_nmi_ipi;\n \tsmp_ops = &pnv_smp_ops;\n \n #ifdef CONFIG_HOTPLUG_CPU\ndiff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c\nindex 33351c6704b1..d9a12102b111 100644\n--- a/arch/powerpc/xmon/xmon.c\n+++ b/arch/powerpc/xmon/xmon.c\n@@ -530,14 +530,19 @@ static int xmon_core(struct pt_regs *regs, int fromipi)\n \n waiting:\n \tsecondary = 1;\n+\tspin_begin();\n \twhile (secondary && !xmon_gate) {\n \t\tif (in_xmon == 0) {\n-\t\t\tif (fromipi)\n+\t\t\tif (fromipi) {\n+\t\t\t\tspin_end();\n \t\t\t\tgoto leave;\n+\t\t\t}\n \t\t\tsecondary = test_and_set_bit(0, &in_xmon);\n \t\t}\n-\t\tbarrier();\n+\t\tspin_cpu_relax();\n+\t\ttouch_nmi_watchdog();\n \t}\n+\tspin_end();\n \n \tif (!secondary && !xmon_gate) {\n \t\t/* we are the first cpu to come in */\n@@ -568,21 +573,25 @@ static int xmon_core(struct pt_regs *regs, int fromipi)\n \t\tmb();\n \t\txmon_gate = 1;\n \t\tbarrier();\n+\t\ttouch_nmi_watchdog();\n \t}\n \n cmdloop:\n \twhile (in_xmon) {\n \t\tif (secondary) {\n+\t\t\tspin_begin();\n \t\t\tif (cpu == xmon_owner) {\n \t\t\t\tif (!test_and_set_bit(0, &xmon_taken)) {\n \t\t\t\t\tsecondary = 0;\n+\t\t\t\t\tspin_end();\n \t\t\t\t\tcontinue;\n \t\t\t\t}\n \t\t\t\t/* missed it */\n \t\t\t\twhile (cpu == xmon_owner)\n-\t\t\t\t\tbarrier();\n+\t\t\t\t\tspin_cpu_relax();\n \t\t\t}\n-\t\t\tbarrier();\n+\t\t\tspin_cpu_relax();\n+\t\t\ttouch_nmi_watchdog();\n \t\t} else {\n \t\t\tcmd = cmds(regs);\n \t\t\tif (cmd != 0) {","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org 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","To":"linuxppc-dev@lists.ozlabs.org, skiboot@lists.ozlabs.org","Message-ID":"<20170914212603.356c66b1@roar.ozlabs.ibm.com>","In-Reply-To":"<20170912160553.13422-3-npiggin@gmail.com>","References":"<20170912160553.13422-1-npiggin@gmail.com>\n\t<20170912160553.13422-3-npiggin@gmail.com>","Organization":"IBM","X-Mailer":"Claws Mail 3.15.0-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","Subject":"Re: [Skiboot] [RFC PATCH 2/2] powerpc/powernv: implement NMI IPIs\n\twith OPAL_SIGNAL_SYSTEM_RESET","X-BeenThere":"skiboot@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Mailing list for skiboot development ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Popple ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"}}]