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GET /api/patches/812944/?format=api
{ "id": 812944, "url": "http://patchwork.ozlabs.org/api/patches/812944/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/20170912160553.13422-2-npiggin@gmail.com/", "project": { "id": 44, "url": "http://patchwork.ozlabs.org/api/projects/44/?format=api", "name": "skiboot firmware development", "link_name": "skiboot", "list_id": "skiboot.lists.ozlabs.org", "list_email": "skiboot@lists.ozlabs.org", "web_url": "http://github.com/open-power/skiboot", "scm_url": "http://github.com/open-power/skiboot", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170912160553.13422-2-npiggin@gmail.com>", "list_archive_url": null, "date": "2017-09-12T16:05:52", "name": "[RFC,1/2] core: implement OPAL_SIGNAL_SYSTEM_RESET with POWER9 scoms", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "c3a2013f9e8f3ee2b43a05b4996cb643f83253b1", "submitter": { "id": 69518, "url": "http://patchwork.ozlabs.org/api/people/69518/?format=api", "name": "Nicholas Piggin", "email": "npiggin@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/20170912160553.13422-2-npiggin@gmail.com/mbox/", "series": [ { "id": 2735, "url": "http://patchwork.ozlabs.org/api/series/2735/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/list/?series=2735", "date": "2017-09-12T16:05:51", "name": "NMI IPI work in progress for Linux and OPAL", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2735/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812944/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812944/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xs8wk49V9z9s7f\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 02:13:26 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xs8wk30JlzDrJm\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 13 Sep 2017 02:13:26 +1000 (AEST)", "from mail-pf0-x22f.google.com (mail-pf0-x22f.google.com\n\t[IPv6:2607:f8b0:400e:c00::22f])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xs8mN1ZhBzDrKC;\n\tWed, 13 Sep 2017 02:06:12 +1000 (AEST)", "by mail-pf0-x22f.google.com with SMTP id e199so19326065pfh.3;\n\tTue, 12 Sep 2017 09:06:12 -0700 (PDT)", "from roar.au.ibm.com (203-219-56-202.tpgi.com.au. [203.219.56.202])\n\tby smtp.gmail.com with ESMTPSA id\n\tq67sm21517424pfg.37.2017.09.12.09.06.06\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 12 Sep 2017 09:06:09 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"P4bFe7yo\"; dkim-atps=neutral", "lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"P4bFe7yo\"; dkim-atps=neutral", "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gmail.com\n\t(client-ip=2607:f8b0:400e:c00::22f; helo=mail-pf0-x22f.google.com;\n\tenvelope-from=npiggin@gmail.com; receiver=<UNKNOWN>)", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"P4bFe7yo\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=mOg1qj3bHDzh6CsPalbmPZHFLiCIq2yv9R+jBz7JQ80=;\n\tb=P4bFe7yodi5eA+GhX7CaXrqUiJnLv4n5UJJfdmfDPacf/wMdvyOTsgd9r/DlcpxcKV\n\tgzaoeKezuuWZi3fyN1puv+vDsrrmg2yNEx6rdqCvLRuBCtw5b4tFc3gL2mTbgkVoWH06\n\tNOWXzWArqKdT4U4MM4X5eOc13k4Wf/o4usPCv7UNs3uafv1NMRWRypXlayOiiR4EZpPX\n\tk6xzVLA8Z36sJnpQtHlySUQJD25kM3hQ/pBoU1XVwD10ooKqzjyGRzlmGfUD+7yg/V9z\n\toZ3Vzg6tSYKEuDroUzeh1LW0Za90th3p2Du8TF04RmbAd1B2VFPZ50juplgWFdPBIPxH\n\tu26Q==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=mOg1qj3bHDzh6CsPalbmPZHFLiCIq2yv9R+jBz7JQ80=;\n\tb=gURPCzvNmnU5UJgMb6Dkc5G63bpcQrD316iGgdNM1Rpur5rsUfb/gbTSVJwzyB8ILB\n\tffMYw96dLIxr3S+RRpiG2hatFKzwFy/D8783G4VrKBjM8Wb2S9CDqRh1ClhH7cWz2jtg\n\tS7gdhE3wvXMb6Fi1Mf49N0pc2ewL6EdyFrmyvQibbNDDd+eGkqNbHi/a7C2U/9oRbBA4\n\tjcO2XhZ1Y6reo86KRIvS+jcJhSDYZtExERZ/LKnyMKiiX7JLjcQhAfo2sp1i0bMpIPCO\n\tdsqffWfhvPvcm1gQrOdHbP2m9dEoxWaj9ywJQx05evxKgGwZ7Bw040Qlc0WII8aiMKzd\n\t0tXA==", "X-Gm-Message-State": "AHPjjUjoDA8+7JMcDXY0a7PaLGczkeBGFx+ABCDCbSnzdnvA2plF4g90\n\tGt8lQtxyjXJSsJ9S", "X-Google-Smtp-Source": "AOwi7QDNDB7PtPQGbLP3cneimoCd1OBQcWdan4kzLiYZrqdFt1LgtPKSrTXi2HhQU8cXRFIdsSEH2w==", "X-Received": "by 10.101.78.12 with SMTP id r12mr2321412pgt.289.1505232370114; \n\tTue, 12 Sep 2017 09:06:10 -0700 (PDT)", "From": "Nicholas Piggin <npiggin@gmail.com>", "To": "linuxppc-dev@lists.ozlabs.org,\n\tskiboot@lists.ozlabs.org", "Date": "Wed, 13 Sep 2017 02:05:52 +1000", "Message-Id": "<20170912160553.13422-2-npiggin@gmail.com>", "X-Mailer": "git-send-email 2.13.3", "In-Reply-To": "<20170912160553.13422-1-npiggin@gmail.com>", "References": "<20170912160553.13422-1-npiggin@gmail.com>", "Subject": "[Skiboot] [RFC PATCH 1/2] core: implement OPAL_SIGNAL_SYSTEM_RESET\n\twith POWER9 scoms", "X-BeenThere": "skiboot@lists.ozlabs.org", "X-Mailman-Version": "2.1.24", "Precedence": "list", "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/skiboot/>", "List-Post": "<mailto:skiboot@lists.ozlabs.org>", "List-Help": "<mailto:skiboot-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Alistair Popple <alistair@popple.id.au>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Skiboot\"\n\t<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "This implements a way to raise system reset interrupts on other\ncores. This has not yet been tested on DD2 or with deeper sleep\nstates.\n---\n core/Makefile.inc | 1 +\n core/sreset.c | 237 ++++++++++++++++++++++++++++++++++++++++++++++++\n hw/xscom.c | 2 +\n include/skiboot.h | 3 +\n platforms/mambo/mambo.c | 3 +-\n 5 files changed, 245 insertions(+), 1 deletion(-)\n create mode 100644 core/sreset.c", "diff": "diff --git a/core/Makefile.inc b/core/Makefile.inc\nindex f2de2f64..16204978 100644\n--- a/core/Makefile.inc\n+++ b/core/Makefile.inc\n@@ -9,6 +9,7 @@ CORE_OBJS += vpd.o hostservices.o platform.o nvram.o nvram-format.o hmi.o\n CORE_OBJS += console-log.o ipmi.o time-utils.o pel.o pool.o errorlog.o\n CORE_OBJS += timer.o i2c.o rtc.o flash.o sensor.o ipmi-opal.o\n CORE_OBJS += flash-subpartition.o bitmap.o buddy.o pci-quirk.o powercap.o psr.o\n+CORE_OBJS += sreset.o\n \n ifeq ($(SKIBOOT_GCOV),1)\n CORE_OBJS += gcov-profiling.o\ndiff --git a/core/sreset.c b/core/sreset.c\nnew file mode 100644\nindex 00000000..ff20fe71\n--- /dev/null\n+++ b/core/sreset.c\n@@ -0,0 +1,237 @@\n+/* Copyright 2017 IBM Corp.\n+ *\n+ * Licensed under the Apache License, Version 2.0 (the \"License\");\n+ * you may not use this file except in compliance with the License.\n+ * You may obtain a copy of the License at\n+ *\n+ * \thttp://www.apache.org/licenses/LICENSE-2.0\n+ *\n+ * Unless required by applicable law or agreed to in writing, software\n+ * distributed under the License is distributed on an \"AS IS\" BASIS,\n+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or\n+ * implied.\n+ * See the License for the specific language governing permissions and\n+ * limitations under the License.\n+ */\n+\n+#include <skiboot.h>\n+#include <cpu.h>\n+#include <fsp.h>\n+#include <psi.h>\n+#include <opal.h>\n+#include <xscom.h>\n+#include <interrupts.h>\n+#include <cec.h>\n+#include <timebase.h>\n+#include <pci.h>\n+#include <chip.h>\n+#include <chiptod.h>\n+#include <ipmi.h>\n+\n+#define P9_RAS_STATUS\t\t\t0x10a02\n+#define P9_RSTAT_QUIESCED(t)\t\tPPC_BITMASK(0 + 8*(t), 3 + 8*(t))\n+#define P9_RAS_MODEREG\t\t\t0x10a9d\n+#define P9_DIRECT_CONTROLS\t\t0x10a9c\n+#define P9_DCTL_STOP(t)\t\t\tPPC_BIT(7 + 8*(t))\n+#define P9_DCTL_CONT(t)\t\t\tPPC_BIT(6 + 8*(t))\n+#define P9_DCTL_SRESET(t)\t\tPPC_BIT(4 + 8*(t))\n+#define P9_DCTL_PWR(t)\t\t\tPPC_BIT(32 + 8*(t))\n+\n+#define P9_CORE_THREAD_STATE\t\t0x10ab3\n+#define P9_CTS_STOP(t)\t\t\tPPC_BIT(56 + (t))\n+\n+#define PPM_GPMMR\t\t\t0xf0100\n+#define PPM_SPWKUP_OTR\t\t\t0xf010a\n+#define SPECIAL_WKUP_DONE\t\tPPC_BIT(1)\n+\n+\n+static int core_set_special_wakeup(struct cpu_thread *cpu)\n+{\n+\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n+\tuint32_t core_id = pir_to_core_id(cpu->pir);\n+\tuint32_t swake_addr;\n+\tuint32_t gpmmr_addr;\n+\tuint64_t val;\n+\tint i;\n+\n+\tswake_addr = XSCOM_ADDR_P9_EC(core_id, PPM_SPWKUP_OTR);\n+\tgpmmr_addr = XSCOM_ADDR_P9_EC(core_id, PPM_GPMMR);\n+\n+\txscom_read(chip_id, swake_addr, &val);\n+\tif (xscom_write(chip_id, swake_addr, PPC_BIT(0))) {\n+\t\tprlog(PR_WARNING, \"SRESET: Unable to write SPWKUP_OTR register\\n\");\n+\t\treturn OPAL_HARDWARE;\n+\t}\n+\txscom_read(chip_id, swake_addr, &val);\n+\n+\tfor (i = 0; i < 100; i++) {\n+\t\tif (xscom_read(chip_id, gpmmr_addr, &val)) {\n+\t\t\tprlog(PR_WARNING, \"SRESET: Unable to read GPMMR register\\n\");\n+\t\t\treturn OPAL_HARDWARE;\n+\t\t}\n+\t\tif (val & SPECIAL_WKUP_DONE)\n+\t\t\treturn 0;\n+\n+\t\ttime_wait_us(1);\n+\t}\n+\n+\txscom_read(chip_id, swake_addr, &val);\n+\txscom_write(chip_id, swake_addr, 0);\n+\txscom_read(chip_id, swake_addr, &val);\n+\n+\tprlog(PR_WARNING, \"SRESET: Special wakeup mode could not be set.\\n\");\n+\treturn OPAL_HARDWARE;\n+}\n+\n+static void core_clear_special_wakeup(struct cpu_thread *cpu)\n+{\n+\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n+\tuint32_t core_id = pir_to_core_id(cpu->pir);\n+\tuint32_t swake_addr;\n+\tuint64_t val;\n+\n+\tswake_addr = XSCOM_ADDR_P9_EC(core_id, PPM_SPWKUP_OTR);\n+\n+\t/* De-assert special wakeup bit */\n+\txscom_read(chip_id, swake_addr, &val);\n+\txscom_write(chip_id, swake_addr, 0);\n+\txscom_read(chip_id, swake_addr, &val);\n+}\n+\n+static int thread_quiesced(struct cpu_thread *cpu)\n+{\n+\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n+\tuint32_t core_id = pir_to_core_id(cpu->pir);\n+\tuint32_t thread_id = pir_to_thread_id(cpu->pir);\n+\tuint32_t ras_addr;\n+\tuint64_t ras_status;\n+\n+\tras_addr = XSCOM_ADDR_P9_EC(core_id, P9_RAS_STATUS);\n+\tif (xscom_read(chip_id, ras_addr, &ras_status)) {\n+\t\tprlog(PR_WARNING, \"SRESET: Unable to read status register\\n\");\n+\t\treturn OPAL_HARDWARE;\n+\t}\n+\n+\tif ((ras_status & P9_RSTAT_QUIESCED(thread_id))\n+\t\t \t== P9_RSTAT_QUIESCED(thread_id))\n+\t\treturn 1;\n+\n+\treturn 0;\n+}\n+\n+static int stop_thread(struct cpu_thread *cpu)\n+{\n+\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n+\tuint32_t core_id = pir_to_core_id(cpu->pir);\n+\tuint32_t thread_id = pir_to_thread_id(cpu->pir);\n+\tuint32_t dctl_addr;\n+\tint i;\n+\n+\tdctl_addr = XSCOM_ADDR_P9_EC(core_id, P9_DIRECT_CONTROLS);\n+\n+\txscom_write(chip_id, dctl_addr, P9_DCTL_STOP(thread_id));\n+\n+\tfor (i = 0; i < 100; i++) {\n+\t\tint rc = thread_quiesced(cpu);\n+\t\tif (rc < 0)\n+\t\t\tbreak;\n+\t\tif (rc)\n+\t\t\treturn 0;\n+\t}\n+\n+\txscom_write(chip_id, dctl_addr, P9_DCTL_CONT(thread_id));\n+\tprlog(PR_WARNING, \"SRESET: Could not quiesce thread\\n\");\n+\treturn OPAL_HARDWARE;\n+}\n+\n+static int sreset_thread(struct cpu_thread *cpu)\n+{\n+\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n+\tuint32_t core_id = pir_to_core_id(cpu->pir);\n+\tuint32_t thread_id = pir_to_thread_id(cpu->pir);\n+\tuint32_t dctl_addr;\n+\tuint32_t cts_addr;\n+\tuint64_t cts_val;\n+\n+\tdctl_addr = XSCOM_ADDR_P9_EC(core_id, P9_DIRECT_CONTROLS);\n+\tcts_addr = XSCOM_ADDR_P9_EC(core_id, P9_CORE_THREAD_STATE);\n+\n+\tif (xscom_read(chip_id, cts_addr, &cts_val)) {\n+\t\tprlog(PR_WARNING, \"SRESET: Unable to read CORE_THREAD_STATE register\\n\");\n+\t\treturn OPAL_HARDWARE;\n+\t}\n+\tif (!(cts_val & P9_CTS_STOP(thread_id))) {\n+\t\t/* Clear SRR1[46:47] */\n+\t\tif (xscom_write(chip_id, dctl_addr, P9_DCTL_PWR(thread_id))) {\n+\t\t\tprlog(PR_WARNING, \"SRESET: Unable to set power saving mode\\n\");\n+\t\t\treturn OPAL_HARDWARE;\n+\t\t}\n+\t}\n+\n+\tif (xscom_write(chip_id, dctl_addr, P9_DCTL_SRESET(thread_id))) {\n+\t\tprlog(PR_WARNING, \"SRESET: Unable to write DIRECT_CONTROLS register\\n\");\n+\t\treturn OPAL_HARDWARE;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+// static struct lock sreset_lock = LOCK_UNLOCKED;\n+\n+static int64_t sreset_cpu(struct cpu_thread *cpu)\n+{\n+\tint rc;\n+\n+\tif (this_cpu() == cpu) {\n+\t\tprlog(PR_WARNING, \"SRESET: Unable to reset self\\n\");\n+\t\treturn OPAL_UNSUPPORTED;\n+\t}\n+\tif (this_cpu()->primary == cpu->primary) {\n+\t\tprlog(PR_WARNING, \"SRESET: Unable to reset threads on same core\\n\");\n+\t\treturn OPAL_PARTIAL;\n+\t}\n+\n+\trc = thread_quiesced(cpu);\n+\tif (rc < 0)\n+\t\treturn rc;\n+\tif (rc) {\n+\t\tprlog(PR_WARNING, \"SRESET: Thread is quiesced already\\n\");\n+\t\treturn OPAL_WRONG_STATE;\n+\t}\n+\n+\trc = core_set_special_wakeup(cpu);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = stop_thread(cpu);\n+\tif (rc) {\n+\t\tcore_clear_special_wakeup(cpu);\n+\t\treturn rc;\n+\t}\n+\n+\trc = sreset_thread(cpu);\n+\n+\tcore_clear_special_wakeup(cpu);\n+\n+\treturn 0;\n+}\n+\n+int64_t signal_system_reset(int cpu_nr)\n+{\n+\tstruct cpu_thread *cpu;\n+\n+\tif (proc_gen != proc_gen_p9)\n+\t\treturn OPAL_UNSUPPORTED;\n+\n+\t/* Reset a single CPU */\n+\tif (cpu_nr >= 0) {\n+\t\tcpu = find_cpu_by_server(cpu_nr);\n+\t\tif (!cpu) {\n+\t\t\tprintf(\"SRESET: could not find cpu by server %d\\n\", cpu_nr);\n+\t\t\treturn OPAL_PARAMETER;\n+\t\t}\n+\t\treturn sreset_cpu(cpu);\n+\t}\n+\tprintf(\"SRESET: unsupported %d\\n\", cpu_nr);\n+\treturn OPAL_PARTIAL;\n+}\ndiff --git a/hw/xscom.c b/hw/xscom.c\nindex 7bd78bf9..f3e04291 100644\n--- a/hw/xscom.c\n+++ b/hw/xscom.c\n@@ -705,6 +705,8 @@ static void xscom_init_chip_info(struct proc_chip *chip)\n \t\tprintf(\"P9 DD%i.%i%d detected\\n\", 0xf & (chip->ec_level >> 4),\n \t\t chip->ec_level & 0xf, rev);\n \t\tchip->ec_rev = rev;\n+\n+\t\topal_register(OPAL_SIGNAL_SYSTEM_RESET, signal_system_reset, 1);\n \t}\n }\n \ndiff --git a/include/skiboot.h b/include/skiboot.h\nindex 4b7d5197..37fd774f 100644\n--- a/include/skiboot.h\n+++ b/include/skiboot.h\n@@ -198,6 +198,9 @@ extern char __sym_map_end[];\n extern unsigned long get_symbol(unsigned long addr,\n \t\t\t\tchar **sym, char **sym_end);\n \n+/* System reset */\n+extern int64_t signal_system_reset(int cpu_nr);\n+\n /* Fast reboot support */\n extern void disable_fast_reboot(const char *reason);\n extern void fast_reboot(void);\ndiff --git a/platforms/mambo/mambo.c b/platforms/mambo/mambo.c\nindex cb6e103c..e306ba5c 100644\n--- a/platforms/mambo/mambo.c\n+++ b/platforms/mambo/mambo.c\n@@ -259,7 +259,8 @@ static int64_t mambo_signal_system_reset(int32_t cpu_nr)\n \n static void mambo_sreset_init(void)\n {\n-\topal_register(OPAL_SIGNAL_SYSTEM_RESET, mambo_signal_system_reset, 1);\n+\tif (0)\n+\t\topal_register(OPAL_SIGNAL_SYSTEM_RESET, mambo_signal_system_reset, 1);\n }\n \n static void mambo_platform_init(void)\n", "prefixes": [ "RFC", "1/2" ] }