[{"id":1767429,"web_url":"http://patchwork.ozlabs.org/comment/1767429/","msgid":"<1505258314.12628.151.camel@kernel.crashing.org>","list_archive_url":null,"date":"2017-09-12T23:18:34","subject":"Re: [Skiboot] [RFC PATCH 1/2] core: implement\n\tOPAL_SIGNAL_SYSTEM_RESET with POWER9 scoms","submitter":{"id":38,"url":"http://patchwork.ozlabs.org/api/people/38/","name":"Benjamin Herrenschmidt","email":"benh@kernel.crashing.org"},"content":"On Wed, 2017-09-13 at 02:05 +1000, Nicholas Piggin wrote:\n> This implements a way to raise system reset interrupts on other\n> cores. This has not yet been tested on DD2 or with deeper sleep\n> states.\n\nReminds me, we need to workaround a bug with XSCOMs on P9\n\nPSCOMs to core in the range 20010A80-20010Ab8 (list below) can fail\noccasionally with an error of 4 (PCB_ADDRESS_ERROR). We need to\n(silently) retry up to 32 times.\n\n> 0000000020010A80 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.SCOMC\n> 0000000020010A81 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.SCOMD\n> 0000000020010A82 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.OCC_SCOMC\n> 0000000020010A83 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.OCC_SCOMD\n> 0000000020010A84 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.SPR_MODE\n> 0000000020010A85 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.CTRL\n> 0000000020010A86 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.SCR0\n> 0000000020010A87 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.SCR1\n> 0000000020010A88 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.SCR2\n> 0000000020010A89 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.SCR3\n> 0000000020010A8E EXP.EC.CC.PCC0.COMMON.SPR_COMMON.V0_HMER\n> 0000000020010A92 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.V0_HMER\n> 0000000020010A8F EXP.EC.CC.PCC0.COMMON.SPR_COMMON.V1_HMER\n> 0000000020010A93 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.V1_HMER\n> 0000000020010A90 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.V2_HMER\n> 0000000020010A94 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.V2_HMER\n> 0000000020010A91 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.V3_HMER\n> 0000000020010A95 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.V3_HMER\n> 0000000020010A96 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.HMEER\n> 0000000020010A97 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.SPATTN\n> 0000000020010A98 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.SPATTN\n> 0000000020010A99 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.SPATTN\n> 0000000020010A9A EXP.EC.CC.PCC0.COMMON.SPR_COMMON.SPATTN_MASK\n> 0000000020010A9B EXP.EC.CC.PCC0.PMC.THREAD_INFO\n> 0000000020010A9C EXP.EC.CC.PCC0.PMC.DIRECT_CONTROLS\n> 0000000020010A9D ECP.PC.PMU.SPR_CORE.RAS_MODEREG\n> 0000000020010A9E EXP.EC.CC.PCC0.COMMON.POW.THROTTLE_CONTROL\n> 0000000020010A9F EXP.EC.CC.PCC0.TFDP.TFP.SPURR_FREQ_DETECT_CYC_CNT\n> 0000000020010AA0 EXP.EC.CC.PCC0.TFDP.TFP.SPURR_FREQ_SCALE\n> 0000000020010AA1 EXP.EC.CC.PCC0.TFDP.TFP.SPURR_FREQ_REF\n> 0000000020010AA2 EXP.EC.CC.PCC0.TFDP.TFP.PWM_EVENTS\n> 0000000020010AA3 EXP.EC.CC.PCC0.TOD_READ\n> 0000000020010AA3 EXP.EC.CC.PCC0.TOD_SYNC000\n> 0000000020010AA3 EXP.EC.CC.PCC0.TOD_SYNC001\n> 0000000020010AA3 EXP.EC.CC.PCC0.TOD_SYNC010\n> 0000000020010AA3 EXP.EC.CC.PCC0.TOD_SYNC011\n> 0000000020010AA3 EXP.EC.CC.PCC0.TOD_SYNC100\n> 0000000020010AA3 EXP.EC.CC.PCC0.TOD_SYNC101\n> 0000000020010AA3 EXP.EC.CC.PCC0.TOD_SYNC110\n> 0000000020010AA3 EXP.EC.CC.PCC0.TOD_SYNC111\n> 0000000020010AA4 EXP.EC.CC.PCC0.COMMON.TFC.TOD_STEP_CHECK\n> 0000000020010AA5 ECP.PC.PMU.SPR_CORE.SHID0\n> 0000000020010AA6 ECP.PC.PMU.SPR_CORE.HV_STATE\n> 0000000020010AA7 ECP.PC.PMU.SPR_CORE.CORE_FUSES\n> 0000000020010AA8 ECP.PC.IMA.IMA_EVENT_MASK\n> 0000000020010AA9 ECP.PC.IMA.IMA_TRACE\n> 0000000020010AAA ECP.PC.T0_PMU_SCOM\n> 0000000020010AAB ECP.PC.T1_PMU_SCOM\n> 0000000020010AAC ECP.PC.T2_PMU_SCOM\n> 0000000020010AAD ECP.PC.T3_PMU_SCOM\n> 0000000020010AAE ECP.PC.PMU.PMUC.SIER_MASK\n> 0000000020010AAF ECP.PC.PMU.PMUC.SRC_MASK\n> 0000000020010AB0 ECP.PC.PMU.SPR_CORE.PMU_SCOMC\n> 0000000020010AB2 ECP.PC.PMU.SPR_CORE.PMU_SCOMC_EN\n> 0000000020010AB3 EXP.EC.CC.PCC0.PMC.CORE_THREAD_STATE\n> 0000000020010AB4 ECP.PC.PMU.SPR_CORE.INV_ERATE\n> 0000000020010AB5 ECP.PC.PMU.SPR_CORE.SPR_CORE_HOLD_OUT\n> 0000000020010AB6 ECP.PC.PMU.SPR_CORE.PMU_HOLD_OUT\n> 0000000020010AB7 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.TFAC_HOLD_OUT\n> 0000000020010AB8 EXP.EC.CC.PCC0.COMMON.SPR_COMMON.SPR_COMMON_HOLD_OUT \n> ---\n> core/Makefile.inc | 1 +\n> core/sreset.c | 237 ++++++++++++++++++++++++++++++++++++++++++++++++\n> hw/xscom.c | 2 +\n> include/skiboot.h | 3 +\n> platforms/mambo/mambo.c | 3 +-\n> 5 files changed, 245 insertions(+), 1 deletion(-)\n> create mode 100644 core/sreset.c\n> \n> diff --git a/core/Makefile.inc b/core/Makefile.inc\n> index f2de2f64..16204978 100644\n> --- a/core/Makefile.inc\n> +++ b/core/Makefile.inc\n> @@ -9,6 +9,7 @@ CORE_OBJS += vpd.o hostservices.o platform.o nvram.o nvram-format.o hmi.o\n> CORE_OBJS += console-log.o ipmi.o time-utils.o pel.o pool.o errorlog.o\n> CORE_OBJS += timer.o i2c.o rtc.o flash.o sensor.o ipmi-opal.o\n> CORE_OBJS += flash-subpartition.o bitmap.o buddy.o pci-quirk.o powercap.o psr.o\n> +CORE_OBJS += sreset.o\n> \n> ifeq ($(SKIBOOT_GCOV),1)\n> CORE_OBJS += gcov-profiling.o\n> diff --git a/core/sreset.c b/core/sreset.c\n> new file mode 100644\n> index 00000000..ff20fe71\n> --- /dev/null\n> +++ b/core/sreset.c\n> @@ -0,0 +1,237 @@\n> +/* Copyright 2017 IBM Corp.\n> + *\n> + * Licensed under the Apache License, Version 2.0 (the \"License\");\n> + * you may not use this file except in compliance with the License.\n> + * You may obtain a copy of the License at\n> + *\n> + * \thttp://www.apache.org/licenses/LICENSE-2.0\n> + *\n> + * Unless required by applicable law or agreed to in writing, software\n> + * distributed under the License is distributed on an \"AS IS\" BASIS,\n> + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or\n> + * implied.\n> + * See the License for the specific language governing permissions and\n> + * limitations under the License.\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define P9_RAS_STATUS\t\t\t0x10a02\n> +#define P9_RSTAT_QUIESCED(t)\t\tPPC_BITMASK(0 + 8*(t), 3 + 8*(t))\n> +#define P9_RAS_MODEREG\t\t\t0x10a9d\n> +#define P9_DIRECT_CONTROLS\t\t0x10a9c\n> +#define P9_DCTL_STOP(t)\t\t\tPPC_BIT(7 + 8*(t))\n> +#define P9_DCTL_CONT(t)\t\t\tPPC_BIT(6 + 8*(t))\n> +#define P9_DCTL_SRESET(t)\t\tPPC_BIT(4 + 8*(t))\n> +#define P9_DCTL_PWR(t)\t\t\tPPC_BIT(32 + 8*(t))\n> +\n> +#define P9_CORE_THREAD_STATE\t\t0x10ab3\n> +#define P9_CTS_STOP(t)\t\t\tPPC_BIT(56 + (t))\n> +\n> +#define PPM_GPMMR\t\t\t0xf0100\n> +#define PPM_SPWKUP_OTR\t\t\t0xf010a\n> +#define SPECIAL_WKUP_DONE\t\tPPC_BIT(1)\n> +\n> +\n> +static int core_set_special_wakeup(struct cpu_thread *cpu)\n> +{\n> +\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n> +\tuint32_t core_id = pir_to_core_id(cpu->pir);\n> +\tuint32_t swake_addr;\n> +\tuint32_t gpmmr_addr;\n> +\tuint64_t val;\n> +\tint i;\n> +\n> +\tswake_addr = XSCOM_ADDR_P9_EC(core_id, PPM_SPWKUP_OTR);\n> +\tgpmmr_addr = XSCOM_ADDR_P9_EC(core_id, PPM_GPMMR);\n> +\n> +\txscom_read(chip_id, swake_addr, &val);\n> +\tif (xscom_write(chip_id, swake_addr, PPC_BIT(0))) {\n> +\t\tprlog(PR_WARNING, \"SRESET: Unable to write SPWKUP_OTR register\\n\");\n> +\t\treturn OPAL_HARDWARE;\n> +\t}\n> +\txscom_read(chip_id, swake_addr, &val);\n> +\n> +\tfor (i = 0; i < 100; i++) {\n> +\t\tif (xscom_read(chip_id, gpmmr_addr, &val)) {\n> +\t\t\tprlog(PR_WARNING, \"SRESET: Unable to read GPMMR register\\n\");\n> +\t\t\treturn OPAL_HARDWARE;\n> +\t\t}\n> +\t\tif (val & SPECIAL_WKUP_DONE)\n> +\t\t\treturn 0;\n> +\n> +\t\ttime_wait_us(1);\n> +\t}\n> +\n> +\txscom_read(chip_id, swake_addr, &val);\n> +\txscom_write(chip_id, swake_addr, 0);\n> +\txscom_read(chip_id, swake_addr, &val);\n> +\n> +\tprlog(PR_WARNING, \"SRESET: Special wakeup mode could not be set.\\n\");\n> +\treturn OPAL_HARDWARE;\n> +}\n> +\n> +static void core_clear_special_wakeup(struct cpu_thread *cpu)\n> +{\n> +\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n> +\tuint32_t core_id = pir_to_core_id(cpu->pir);\n> +\tuint32_t swake_addr;\n> +\tuint64_t val;\n> +\n> +\tswake_addr = XSCOM_ADDR_P9_EC(core_id, PPM_SPWKUP_OTR);\n> +\n> +\t/* De-assert special wakeup bit */\n> +\txscom_read(chip_id, swake_addr, &val);\n> +\txscom_write(chip_id, swake_addr, 0);\n> +\txscom_read(chip_id, swake_addr, &val);\n> +}\n> +\n> +static int thread_quiesced(struct cpu_thread *cpu)\n> +{\n> +\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n> +\tuint32_t core_id = pir_to_core_id(cpu->pir);\n> +\tuint32_t thread_id = pir_to_thread_id(cpu->pir);\n> +\tuint32_t ras_addr;\n> +\tuint64_t ras_status;\n> +\n> +\tras_addr = XSCOM_ADDR_P9_EC(core_id, P9_RAS_STATUS);\n> +\tif (xscom_read(chip_id, ras_addr, &ras_status)) {\n> +\t\tprlog(PR_WARNING, \"SRESET: Unable to read status register\\n\");\n> +\t\treturn OPAL_HARDWARE;\n> +\t}\n> +\n> +\tif ((ras_status & P9_RSTAT_QUIESCED(thread_id))\n> +\t\t \t== P9_RSTAT_QUIESCED(thread_id))\n> +\t\treturn 1;\n> +\n> +\treturn 0;\n> +}\n> +\n> +static int stop_thread(struct cpu_thread *cpu)\n> +{\n> +\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n> +\tuint32_t core_id = pir_to_core_id(cpu->pir);\n> +\tuint32_t thread_id = pir_to_thread_id(cpu->pir);\n> +\tuint32_t dctl_addr;\n> +\tint i;\n> +\n> +\tdctl_addr = XSCOM_ADDR_P9_EC(core_id, P9_DIRECT_CONTROLS);\n> +\n> +\txscom_write(chip_id, dctl_addr, P9_DCTL_STOP(thread_id));\n> +\n> +\tfor (i = 0; i < 100; i++) {\n> +\t\tint rc = thread_quiesced(cpu);\n> +\t\tif (rc < 0)\n> +\t\t\tbreak;\n> +\t\tif (rc)\n> +\t\t\treturn 0;\n> +\t}\n> +\n> +\txscom_write(chip_id, dctl_addr, P9_DCTL_CONT(thread_id));\n> +\tprlog(PR_WARNING, \"SRESET: Could not quiesce thread\\n\");\n> +\treturn OPAL_HARDWARE;\n> +}\n> +\n> +static int sreset_thread(struct cpu_thread *cpu)\n> +{\n> +\tuint32_t chip_id = pir_to_chip_id(cpu->pir);\n> +\tuint32_t core_id = pir_to_core_id(cpu->pir);\n> +\tuint32_t thread_id = pir_to_thread_id(cpu->pir);\n> +\tuint32_t dctl_addr;\n> +\tuint32_t cts_addr;\n> +\tuint64_t cts_val;\n> +\n> +\tdctl_addr = XSCOM_ADDR_P9_EC(core_id, P9_DIRECT_CONTROLS);\n> +\tcts_addr = XSCOM_ADDR_P9_EC(core_id, P9_CORE_THREAD_STATE);\n> +\n> +\tif (xscom_read(chip_id, cts_addr, &cts_val)) {\n> +\t\tprlog(PR_WARNING, \"SRESET: Unable to read CORE_THREAD_STATE register\\n\");\n> +\t\treturn OPAL_HARDWARE;\n> +\t}\n> +\tif (!(cts_val & P9_CTS_STOP(thread_id))) {\n> +\t\t/* Clear SRR1[46:47] */\n> +\t\tif (xscom_write(chip_id, dctl_addr, P9_DCTL_PWR(thread_id))) {\n> +\t\t\tprlog(PR_WARNING, \"SRESET: Unable to set power saving mode\\n\");\n> +\t\t\treturn OPAL_HARDWARE;\n> +\t\t}\n> +\t}\n> +\n> +\tif (xscom_write(chip_id, dctl_addr, P9_DCTL_SRESET(thread_id))) {\n> +\t\tprlog(PR_WARNING, \"SRESET: Unable to write DIRECT_CONTROLS register\\n\");\n> +\t\treturn OPAL_HARDWARE;\n> +\t}\n> +\n> +\treturn 0;\n> +}\n> +\n> +// static struct lock sreset_lock = LOCK_UNLOCKED;\n> +\n> +static int64_t sreset_cpu(struct cpu_thread *cpu)\n> +{\n> +\tint rc;\n> +\n> +\tif (this_cpu() == cpu) {\n> +\t\tprlog(PR_WARNING, \"SRESET: Unable to reset self\\n\");\n> +\t\treturn OPAL_UNSUPPORTED;\n> +\t}\n> +\tif (this_cpu()->primary == cpu->primary) {\n> +\t\tprlog(PR_WARNING, \"SRESET: Unable to reset threads on same core\\n\");\n> +\t\treturn OPAL_PARTIAL;\n> +\t}\n> +\n> +\trc = thread_quiesced(cpu);\n> +\tif (rc < 0)\n> +\t\treturn rc;\n> +\tif (rc) {\n> +\t\tprlog(PR_WARNING, \"SRESET: Thread is quiesced already\\n\");\n> +\t\treturn OPAL_WRONG_STATE;\n> +\t}\n> +\n> +\trc = core_set_special_wakeup(cpu);\n> +\tif (rc)\n> +\t\treturn rc;\n> +\n> +\trc = stop_thread(cpu);\n> +\tif (rc) {\n> +\t\tcore_clear_special_wakeup(cpu);\n> +\t\treturn rc;\n> +\t}\n> +\n> +\trc = sreset_thread(cpu);\n> +\n> +\tcore_clear_special_wakeup(cpu);\n> +\n> +\treturn 0;\n> +}\n> +\n> +int64_t signal_system_reset(int cpu_nr)\n> +{\n> +\tstruct cpu_thread *cpu;\n> +\n> +\tif (proc_gen != proc_gen_p9)\n> +\t\treturn OPAL_UNSUPPORTED;\n> +\n> +\t/* Reset a single CPU */\n> +\tif (cpu_nr >= 0) {\n> +\t\tcpu = find_cpu_by_server(cpu_nr);\n> +\t\tif (!cpu) {\n> +\t\t\tprintf(\"SRESET: could not find cpu by server %d\\n\", cpu_nr);\n> +\t\t\treturn OPAL_PARAMETER;\n> +\t\t}\n> +\t\treturn sreset_cpu(cpu);\n> +\t}\n> +\tprintf(\"SRESET: unsupported %d\\n\", cpu_nr);\n> +\treturn OPAL_PARTIAL;\n> +}\n> diff --git a/hw/xscom.c b/hw/xscom.c\n> index 7bd78bf9..f3e04291 100644\n> --- a/hw/xscom.c\n> +++ b/hw/xscom.c\n> @@ -705,6 +705,8 @@ static void xscom_init_chip_info(struct proc_chip *chip)\n> \t\tprintf(\"P9 DD%i.%i%d detected\\n\", 0xf & (chip->ec_level >> 4),\n> \t\t chip->ec_level & 0xf, rev);\n> \t\tchip->ec_rev = rev;\n> +\n> +\t\topal_register(OPAL_SIGNAL_SYSTEM_RESET, signal_system_reset, 1);\n> \t}\n> }\n> \n> diff --git a/include/skiboot.h b/include/skiboot.h\n> index 4b7d5197..37fd774f 100644\n> --- a/include/skiboot.h\n> +++ b/include/skiboot.h\n> @@ -198,6 +198,9 @@ extern char __sym_map_end[];\n> extern unsigned long get_symbol(unsigned long addr,\n> \t\t\t\tchar **sym, char **sym_end);\n> \n> +/* System reset */\n> +extern int64_t signal_system_reset(int cpu_nr);\n> +\n> /* Fast reboot support */\n> extern void disable_fast_reboot(const char *reason);\n> extern void fast_reboot(void);\n> diff --git a/platforms/mambo/mambo.c b/platforms/mambo/mambo.c\n> index cb6e103c..e306ba5c 100644\n> --- a/platforms/mambo/mambo.c\n> +++ b/platforms/mambo/mambo.c\n> @@ -259,7 +259,8 @@ static int64_t mambo_signal_system_reset(int32_t cpu_nr)\n> \n> static void mambo_sreset_init(void)\n> {\n> -\topal_register(OPAL_SIGNAL_SYSTEM_RESET, mambo_signal_system_reset, 1);\n> +\tif (0)\n> +\t\topal_register(OPAL_SIGNAL_SYSTEM_RESET, mambo_signal_system_reset, 1);\n> }\n> \n> static void mambo_platform_init(void)","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsLMs132hz9rxl\n\tfor ;\n\tWed, 13 Sep 2017 09:19:05 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xsLMs02xqzDrMg\n\tfor ;\n\tWed, 13 Sep 2017 09:19:05 +1000 (AEST)","from gate.crashing.org (gate.crashing.org [63.228.1.57])\n\t(using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xsLMV5fnkzDrJg;\n\tWed, 13 Sep 2017 09:18:46 +1000 (AEST)","from localhost (localhost.localdomain [127.0.0.1])\n\tby gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8CNIYB3000786;\n\tTue, 12 Sep 2017 18:18:35 -0500"],"Authentication-Results":"ozlabs.org; spf=permerror (mailfrom)\n\tsmtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57;\n\thelo=gate.crashing.org; envelope-from=benh@kernel.crashing.org;\n\treceiver=)","Message-ID":"<1505258314.12628.151.camel@kernel.crashing.org>","From":"Benjamin Herrenschmidt ","To":"Nicholas Piggin , linuxppc-dev@lists.ozlabs.org,\n\tskiboot@lists.ozlabs.org","Date":"Wed, 13 Sep 2017 09:18:34 +1000","In-Reply-To":"<20170912160553.13422-2-npiggin@gmail.com>","References":"<20170912160553.13422-1-npiggin@gmail.com>\n\t<20170912160553.13422-2-npiggin@gmail.com>","X-Mailer":"Evolution 3.24.5 (3.24.5-1.fc26) ","Mime-Version":"1.0","Subject":"Re: [Skiboot] [RFC PATCH 1/2] core: implement\n\tOPAL_SIGNAL_SYSTEM_RESET with POWER9 scoms","X-BeenThere":"skiboot@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Mailing list for skiboot development ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alistair Popple ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"}},{"id":1767887,"web_url":"http://patchwork.ozlabs.org/comment/1767887/","msgid":"<20170913232716.138ca093@roar.ozlabs.ibm.com>","list_archive_url":null,"date":"2017-09-13T13:27:16","subject":"Re: [Skiboot] [RFC PATCH 1/2] core: implement\n\tOPAL_SIGNAL_SYSTEM_RESET with POWER9 scoms","submitter":{"id":69518,"url":"http://patchwork.ozlabs.org/api/people/69518/","name":"Nicholas Piggin","email":"npiggin@gmail.com"},"content":"On Wed, 13 Sep 2017 09:18:34 +1000\nBenjamin Herrenschmidt wrote:\n\n> On Wed, 2017-09-13 at 02:05 +1000, Nicholas Piggin wrote:\n> > This implements a way to raise system reset interrupts on other\n> > cores. This has not yet been tested on DD2 or with deeper sleep\n> > states. \n> \n> Reminds me, we need to workaround a bug with XSCOMs on P9\n> \n> PSCOMs to core in the range 20010A80-20010Ab8 (list below) can fail\n> occasionally with an error of 4 (PCB_ADDRESS_ERROR). We need to\n> (silently) retry up to 32 times.\n\n[snip]\n\nSo, just put a loop into xscom_read and xscom_write for those\naddresses for P9 chips?\n\nThanks,\nNick","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsjMK2NFsz9sNV\n\tfor ;\n\tWed, 13 Sep 2017 23:34:53 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xsjMK15h6zDrVt\n\tfor ;\n\tWed, 13 Sep 2017 23:34:53 +1000 (AEST)","from mail-pg0-x234.google.com (mail-pg0-x234.google.com\n\t[IPv6:2607:f8b0:400e:c05::234])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xsjJh3GjczDrFt;\n\tWed, 13 Sep 2017 23:32:36 +1000 (AEST)","by mail-pg0-x234.google.com with SMTP id j16so430046pga.1;\n\tWed, 13 Sep 2017 06:32:36 -0700 (PDT)","from roar.ozlabs.ibm.com (203-219-56-202.tpgi.com.au.\n\t[203.219.56.202]) by smtp.gmail.com with ESMTPSA id\n\tt125sm23966499pgc.50.2017.09.13.06.32.30\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 13 Sep 2017 06:32:33 -0700 (PDT)"],"Authentication-Results":["ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"IS4ukP65\"; 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x86_64-pc-linux-gnu)","MIME-Version":"1.0","Subject":"Re: [Skiboot] [RFC PATCH 1/2] core: implement\n\tOPAL_SIGNAL_SYSTEM_RESET with POWER9 scoms","X-BeenThere":"skiboot@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Mailing list for skiboot development ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"skiboot@lists.ozlabs.org, linuxppc-dev@lists.ozlabs.org,\n\tAlistair Popple ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"}},{"id":1768305,"web_url":"http://patchwork.ozlabs.org/comment/1768305/","msgid":"<1505356038.12628.179.camel@kernel.crashing.org>","list_archive_url":null,"date":"2017-09-14T02:27:18","subject":"Re: [Skiboot] [RFC PATCH 1/2] core: implement\n\tOPAL_SIGNAL_SYSTEM_RESET with POWER9 scoms","submitter":{"id":38,"url":"http://patchwork.ozlabs.org/api/people/38/","name":"Benjamin Herrenschmidt","email":"benh@kernel.crashing.org"},"content":"On Wed, 2017-09-13 at 23:27 +1000, Nicholas Piggin wrote:\n> On Wed, 13 Sep 2017 09:18:34 +1000\n> Benjamin Herrenschmidt wrote:\n> \n> > On Wed, 2017-09-13 at 02:05 +1000, Nicholas Piggin wrote:\n> > > This implements a way to raise system reset interrupts on other\n> > > cores. This has not yet been tested on DD2 or with deeper sleep\n> > > states. \n> > \n> > Reminds me, we need to workaround a bug with XSCOMs on P9\n> > \n> > PSCOMs to core in the range 20010A80-20010Ab8 (list below) can fail\n> > occasionally with an error of 4 (PCB_ADDRESS_ERROR). We need to\n> > (silently) retry up to 32 times.\n> \n> [snip]\n> \n> So, just put a loop into xscom_read and xscom_write for those\n> addresses for P9 chips?\n\nRight. Well, the top bit of the address needs filtering since it's the\ntarget core, ie, 0x20 is core 0, 0x21 is core 1 etc... to 0x37.\n\nCheers,\nBen.","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xt2Vr6f7Zz9t2V\n\tfor ;\n\tThu, 14 Sep 2017 12:27:32 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xt2Vr5gX9zDqBc\n\tfor ;\n\tThu, 14 Sep 2017 12:27:32 +1000 (AEST)","from gate.crashing.org (gate.crashing.org [63.228.1.57])\n\t(using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xt2Vk5mNYzDq78;\n\tThu, 14 Sep 2017 12:27:26 +1000 (AEST)","from localhost (localhost.localdomain [127.0.0.1])\n\tby gate.crashing.org (8.14.1/8.13.8) with ESMTP id v8E2RIX1031733;\n\tWed, 13 Sep 2017 21:27:19 -0500"],"Authentication-Results":"ozlabs.org; spf=permerror (mailfrom)\n\tsmtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57;\n\thelo=gate.crashing.org; envelope-from=benh@kernel.crashing.org;\n\treceiver=)","Message-ID":"<1505356038.12628.179.camel@kernel.crashing.org>","From":"Benjamin Herrenschmidt ","To":"Nicholas Piggin ","Date":"Thu, 14 Sep 2017 12:27:18 +1000","In-Reply-To":"<20170913232716.138ca093@roar.ozlabs.ibm.com>","References":"<20170912160553.13422-1-npiggin@gmail.com>\n\t<20170912160553.13422-2-npiggin@gmail.com>\n\t<1505258314.12628.151.camel@kernel.crashing.org>\n\t<20170913232716.138ca093@roar.ozlabs.ibm.com>","X-Mailer":"Evolution 3.24.5 (3.24.5-1.fc26) ","Mime-Version":"1.0","Subject":"Re: [Skiboot] [RFC PATCH 1/2] core: implement\n\tOPAL_SIGNAL_SYSTEM_RESET with POWER9 scoms","X-BeenThere":"skiboot@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Mailing list for skiboot development ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"skiboot@lists.ozlabs.org, linuxppc-dev@lists.ozlabs.org,\n\tAlistair Popple ","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"}}]