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GET /api/patches/812505/?format=api
{ "id": 812505, "url": "http://patchwork.ozlabs.org/api/patches/812505/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911172022.4738-17-eblake@redhat.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170911172022.4738-17-eblake@redhat.com>", "list_archive_url": null, "date": "2017-09-11T17:20:00", "name": "[v7,16/38] libqos: Use explicit QTestState for ahci operations", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ee3cf73f3326339cc6a87fb5c4ea3017339322b1", "submitter": { "id": 6591, "url": "http://patchwork.ozlabs.org/api/people/6591/?format=api", "name": "Eric Blake", "email": "eblake@redhat.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911172022.4738-17-eblake@redhat.com/mbox/", "series": [ { "id": 2534, "url": "http://patchwork.ozlabs.org/api/series/2534/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2534", "date": "2017-09-11T17:19:47", "name": "Preliminary libqtest cleanups", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/2534/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812505/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812505/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com", "ext-mx01.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=eblake@redhat.com" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xrb5s4jzmz9s7F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 12 Sep 2017 03:49:21 +1000 (AEST)", "from localhost ([::1]:59475 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drSpj-0008G1-LF\n\tfor incoming@patchwork.ozlabs.org; Mon, 11 Sep 2017 13:49:19 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:38597)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <eblake@redhat.com>) id 1drSOW-0007Ue-Nr\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:21:16 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <eblake@redhat.com>) id 1drSOS-0001Fv-6u\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:21:12 -0400", "from mx1.redhat.com ([209.132.183.28]:40284)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <eblake@redhat.com>)\n\tid 1drSOL-0001D3-NC; Mon, 11 Sep 2017 13:21:01 -0400", "from smtp.corp.redhat.com\n\t(int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id D7CBFCC989;\n\tMon, 11 Sep 2017 17:21:00 +0000 (UTC)", "from red.redhat.com (ovpn-120-44.rdu2.redhat.com [10.10.120.44])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 561C95D9CA;\n\tMon, 11 Sep 2017 17:20:57 +0000 (UTC)" ], "DMARC-Filter": "OpenDMARC Filter v1.3.2 mx1.redhat.com D7CBFCC989", "From": "Eric Blake <eblake@redhat.com>", "To": "qemu-devel@nongnu.org", "Date": "Mon, 11 Sep 2017 12:20:00 -0500", "Message-Id": "<20170911172022.4738-17-eblake@redhat.com>", "In-Reply-To": "<20170911172022.4738-1-eblake@redhat.com>", "References": "<20170911172022.4738-1-eblake@redhat.com>", "X-Scanned-By": "MIMEDefang 2.79 on 10.5.11.14", "X-Greylist": "Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.25]);\n\tMon, 11 Sep 2017 17:21:01 +0000 (UTC)", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "209.132.183.28", "Subject": "[Qemu-devel] [PATCH v7 16/38] libqos: Use explicit QTestState for\n\tahci operations", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "pbonzini@redhat.com, thuth@redhat.com, John Snow <jsnow@redhat.com>,\n\tarmbru@redhat.com, \"open list:IDE\" <qemu-block@nongnu.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "Drop one more client of global_qtest by teaching all ahci test\nfunctionality to pass in an explicit QTestState. The state was\nalready available, so no callers had to be adjusted.\n\nSigned-off-by: Eric Blake <eblake@redhat.com>\n\n---\nv7: split libqos changes from test-ahci\n---\n tests/libqos/ahci.c | 45 +++++++++++++++++++++++----------------------\n 1 file changed, 23 insertions(+), 22 deletions(-)", "diff": "diff --git a/tests/libqos/ahci.c b/tests/libqos/ahci.c\nindex 790ef991b3..ba79cd77a0 100644\n--- a/tests/libqos/ahci.c\n+++ b/tests/libqos/ahci.c\n@@ -283,7 +283,8 @@ void ahci_hba_enable(AHCIQState *ahci)\n /* Allocate Memory for the Command List Buffer & FIS Buffer */\n /* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */\n ahci->port[i].clb = ahci_alloc(ahci, num_cmd_slots * 0x20);\n- qmemset(ahci->port[i].clb, 0x00, num_cmd_slots * 0x20);\n+ qtest_memset(ahci->parent->qts, ahci->port[i].clb, 0x00,\n+ num_cmd_slots * 0x20);\n g_test_message(\"CLB: 0x%08\" PRIx64, ahci->port[i].clb);\n ahci_px_wreg(ahci, i, AHCI_PX_CLB, ahci->port[i].clb);\n g_assert_cmphex(ahci->port[i].clb, ==,\n@@ -291,7 +292,7 @@ void ahci_hba_enable(AHCIQState *ahci)\n\n /* PxFB space ... 0x100, as in 4.2.1 p 35 */\n ahci->port[i].fb = ahci_alloc(ahci, 0x100);\n- qmemset(ahci->port[i].fb, 0x00, 0x100);\n+ qtest_memset(ahci->parent->qts, ahci->port[i].fb, 0x00, 0x100);\n g_test_message(\"FB: 0x%08\" PRIx64, ahci->port[i].fb);\n ahci_px_wreg(ahci, i, AHCI_PX_FB, ahci->port[i].fb);\n g_assert_cmphex(ahci->port[i].fb, ==,\n@@ -397,7 +398,7 @@ void ahci_port_clear(AHCIQState *ahci, uint8_t port)\n g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0);\n\n /* Wipe the FIS-Receive Buffer */\n- qmemset(ahci->port[port].fb, 0x00, 0x100);\n+ qtest_memset(ahci->parent->qts, ahci->port[port].fb, 0x00, 0x100);\n }\n\n /**\n@@ -466,7 +467,7 @@ void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot)\n RegD2HFIS *d2h = g_malloc0(0x20);\n uint32_t reg;\n\n- memread(ahci->port[port].fb + 0x40, d2h, 0x20);\n+ qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x40, d2h, 0x20);\n g_assert_cmphex(d2h->fis_type, ==, 0x34);\n\n reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD);\n@@ -484,7 +485,7 @@ void ahci_port_check_pio_sanity(AHCIQState *ahci, uint8_t port,\n /* We cannot check the Status or E_Status registers, because\n * the status may have again changed between the PIO Setup FIS\n * and the conclusion of the command with the D2H Register FIS. */\n- memread(ahci->port[port].fb + 0x20, pio, 0x20);\n+ qtest_memread(ahci->parent->qts, ahci->port[port].fb + 0x20, pio, 0x20);\n g_assert_cmphex(pio->fis_type, ==, 0x5f);\n\n /* BUG: PIO Setup FIS as utilized by QEMU tries to fit the entire\n@@ -516,7 +517,7 @@ void ahci_get_command_header(AHCIQState *ahci, uint8_t port,\n {\n uint64_t ba = ahci->port[port].clb;\n ba += slot * sizeof(AHCICommandHeader);\n- memread(ba, cmd, sizeof(AHCICommandHeader));\n+ qtest_memread(ahci->parent->qts, ba, cmd, sizeof(AHCICommandHeader));\n\n cmd->flags = le16_to_cpu(cmd->flags);\n cmd->prdtl = le16_to_cpu(cmd->prdtl);\n@@ -537,7 +538,7 @@ void ahci_set_command_header(AHCIQState *ahci, uint8_t port,\n tmp.prdbc = cpu_to_le32(cmd->prdbc);\n tmp.ctba = cpu_to_le64(cmd->ctba);\n\n- memwrite(ba, &tmp, sizeof(AHCICommandHeader));\n+ qtest_memwrite(ahci->parent->qts, ba, &tmp, sizeof(AHCICommandHeader));\n }\n\n void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot)\n@@ -575,7 +576,7 @@ void ahci_write_fis(AHCIQState *ahci, AHCICommand *cmd)\n tmp.count = cpu_to_le16(tmp.count);\n }\n\n- memwrite(addr, &tmp, sizeof(tmp));\n+ qtest_memwrite(ahci->parent->qts, addr, &tmp, sizeof(tmp));\n }\n\n unsigned ahci_pick_cmd(AHCIQState *ahci, uint8_t port)\n@@ -636,7 +637,7 @@ void ahci_exec(AHCIQState *ahci, uint8_t port,\n if (opts->size && !opts->buffer) {\n opts->buffer = ahci_alloc(ahci, opts->size);\n g_assert(opts->buffer);\n- qmemset(opts->buffer, 0x00, opts->size);\n+ qtest_memset(ahci->parent->qts, opts->buffer, 0x00, opts->size);\n }\n\n /* Command creation */\n@@ -661,15 +662,15 @@ void ahci_exec(AHCIQState *ahci, uint8_t port,\n ahci_command_commit(ahci, cmd, port);\n ahci_command_issue_async(ahci, cmd);\n if (opts->error) {\n- qmp_eventwait(\"STOP\");\n+ qtest_qmp_eventwait(ahci->parent->qts, \"STOP\");\n }\n if (opts->mid_cb) {\n rc = opts->mid_cb(ahci, cmd, opts);\n g_assert_cmpint(rc, ==, 0);\n }\n if (opts->error) {\n- qmp_async(\"{'execute':'cont' }\");\n- qmp_eventwait(\"RESUME\");\n+ qtest_async_qmp(ahci->parent->qts, \"{'execute':'cont' }\");\n+ qtest_qmp_eventwait(ahci->parent->qts, \"RESUME\");\n }\n\n /* Wait for command to complete and verify sanity */\n@@ -697,7 +698,7 @@ AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port,\n ahci_command_adjust(cmd, sector, buffer, bufsize, 0);\n ahci_command_commit(ahci, cmd, port);\n ahci_command_issue_async(ahci, cmd);\n- qmp_eventwait(\"STOP\");\n+ qtest_qmp_eventwait(ahci->parent->qts, \"STOP\");\n\n return cmd;\n }\n@@ -706,8 +707,8 @@ AHCICommand *ahci_guest_io_halt(AHCIQState *ahci, uint8_t port,\n void ahci_guest_io_resume(AHCIQState *ahci, AHCICommand *cmd)\n {\n /* Complete the command */\n- qmp_async(\"{'execute':'cont' }\");\n- qmp_eventwait(\"RESUME\");\n+ qtest_async_qmp(ahci->parent->qts, \"{'execute':'cont' }\");\n+ qtest_qmp_eventwait(ahci->parent->qts, \"RESUME\");\n ahci_command_wait(ahci, cmd);\n ahci_command_verify(ahci, cmd);\n ahci_command_free(cmd);\n@@ -754,16 +755,16 @@ void ahci_io(AHCIQState *ahci, uint8_t port, uint8_t ide_cmd,\n g_assert(props);\n ptr = ahci_alloc(ahci, bufsize);\n g_assert(!bufsize || ptr);\n- qmemset(ptr, 0x00, bufsize);\n+ qtest_memset(ahci->parent->qts, ptr, 0x00, bufsize);\n\n if (bufsize && props->write) {\n- bufwrite(ptr, buffer, bufsize);\n+ qtest_bufwrite(ahci->parent->qts, ptr, buffer, bufsize);\n }\n\n ahci_guest_io(ahci, port, ide_cmd, ptr, bufsize, sector);\n\n if (bufsize && props->read) {\n- bufread(ptr, buffer, bufsize);\n+ qtest_bufread(ahci->parent->qts, ptr, buffer, bufsize);\n }\n\n ahci_free(ahci, ptr);\n@@ -901,7 +902,7 @@ static int copy_buffer(AHCIQState *ahci, AHCICommand *cmd,\n const AHCIOpts *opts)\n {\n unsigned char *rx = opts->opaque;\n- bufread(opts->buffer, rx, opts->size);\n+ qtest_bufread(ahci->parent->qts, opts->buffer, rx, opts->size);\n return 0;\n }\n\n@@ -1141,7 +1142,7 @@ void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port)\n ahci_write_fis(ahci, cmd);\n /* Then ATAPI CMD, if needed */\n if (cmd->props->atapi) {\n- memwrite(table_ptr + 0x40, cmd->atapi_cmd, 16);\n+ qtest_memwrite(ahci->parent->qts, table_ptr + 0x40, cmd->atapi_cmd, 16);\n }\n\n /* Construct and write the PRDs to the command table */\n@@ -1162,8 +1163,8 @@ void ahci_command_commit(AHCIQState *ahci, AHCICommand *cmd, uint8_t port)\n prd.dbc |= cpu_to_le32(0x80000000); /* Request DPS Interrupt */\n\n /* Commit the PRD entry to the Command Table */\n- memwrite(table_ptr + 0x80 + (i * sizeof(PRD)),\n- &prd, sizeof(PRD));\n+ qtest_memwrite(ahci->parent->qts, table_ptr + 0x80 + (i * sizeof(PRD)),\n+ &prd, sizeof(PRD));\n }\n\n /* Bookmark the PRDTL and CTBA values */\n", "prefixes": [ "v7", "16/38" ] }