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GET /api/patches/812485/?format=api
{ "id": 812485, "url": "http://patchwork.ozlabs.org/api/patches/812485/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911171235.29331-17-clg@kaod.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170911171235.29331-17-clg@kaod.org>", "list_archive_url": null, "date": "2017-09-11T17:12:30", "name": "[RFC,v2,16/21] spapr: add a XIVE object to the sPAPR machine", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "99aa2edc6e9ecc16f6def44aa1c071ffe206f06c", "submitter": { "id": 68548, "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api", "name": "Cédric Le Goater", "email": "clg@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911171235.29331-17-clg@kaod.org/mbox/", "series": [ { "id": 2526, "url": "http://patchwork.ozlabs.org/api/series/2526/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2526", "date": "2017-09-11T17:12:14", "name": "Guest exploitation of the XIVE interrupt controller (POWER9)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2526/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812485/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812485/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xrZnC53xDz9s81\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 12 Sep 2017 03:34:55 +1000 (AEST)", "from localhost ([::1]:59388 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drSbl-0003CO-NC\n\tfor incoming@patchwork.ozlabs.org; Mon, 11 Sep 2017 13:34:53 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:35692)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <clg@kaod.org>) id 1drSIL-0001sc-Ti\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:14:54 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <clg@kaod.org>) id 1drSIH-0004l7-B8\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:14:49 -0400", "from 8.mo2.mail-out.ovh.net ([188.165.52.147]:45433)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <clg@kaod.org>) id 1drSIH-0004km-1D\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:14:45 -0400", "from player770.ha.ovh.net (b6.ovh.net [213.186.33.56])\n\tby mo2.mail-out.ovh.net (Postfix) with ESMTP id 1529EAB24B\n\tfor <qemu-devel@nongnu.org>; Mon, 11 Sep 2017 19:14:44 +0200 (CEST)", "from zorba.kaod.org.com (LFbn-1-2231-173.w90-76.abo.wanadoo.fr\n\t[90.76.52.173]) (Authenticated sender: clg@kaod.org)\n\tby player770.ha.ovh.net (Postfix) with ESMTPSA id D8A623C006C;\n\tMon, 11 Sep 2017 19:14:36 +0200 (CEST)" ], "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "To": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org,\n\tDavid Gibson <david@gibson.dropbear.id.au>,\n\tBenjamin Herrenschmidt <benh@kernel.crashing.org>,\n\tAlexey Kardashevskiy <aik@ozlabs.ru>, Alexander Graf <agraf@suse.de>", "Date": "Mon, 11 Sep 2017 19:12:30 +0200", "Message-Id": "<20170911171235.29331-17-clg@kaod.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170911171235.29331-1-clg@kaod.org>", "References": "<20170911171235.29331-1-clg@kaod.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "X-Ovh-Tracer-Id": "14160443129388567379", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "gggruggvucftvghtrhhoucdtuddrfeelledrgedtgdduudehucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm", "Content-Transfer-Encoding": "quoted-printable", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "188.165.52.147", "Subject": "[Qemu-devel] [RFC PATCH v2 16/21] spapr: add a XIVE object to the\n\tsPAPR machine", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "If the machine supports XIVE (POWER9 CPU), create a XIVE object. The\nCAS negotiation process will decide which model (legacy or XIVE) will\nbe used for the interrupt controller depending on the guest\ncapabilities.\n\nAlso extend the number of provisionned IRQs with the number of CPUs,\nthis is required for XIVE which allocates one IRQ number for each IPI.\n\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n hw/ppc/spapr.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++--\n include/hw/ppc/spapr.h | 2 ++\n 2 files changed, 63 insertions(+), 2 deletions(-)", "diff": "diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c\nindex 5d69df928434..b6577dbecdea 100644\n--- a/hw/ppc/spapr.c\n+++ b/hw/ppc/spapr.c\n@@ -44,6 +44,7 @@\n #include \"mmu-hash64.h\"\n #include \"mmu-book3s-v3.h\"\n #include \"qom/cpu.h\"\n+#include \"target/ppc/cpu-models.h\"\n \n #include \"hw/boards.h\"\n #include \"hw/ppc/ppc.h\"\n@@ -54,6 +55,7 @@\n #include \"hw/ppc/spapr_vio.h\"\n #include \"hw/pci-host/spapr.h\"\n #include \"hw/ppc/xics.h\"\n+#include \"hw/ppc/spapr_xive.h\"\n #include \"hw/pci/msi.h\"\n \n #include \"hw/pci/pci.h\"\n@@ -202,6 +204,35 @@ static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)\n }\n }\n \n+static sPAPRXive *spapr_spapr_xive_create(sPAPRMachineState *spapr, int nr_irqs,\n+ int nr_servers, Error **errp)\n+{\n+ Error *local_err = NULL;\n+ Object *obj;\n+\n+ obj = object_new(TYPE_SPAPR_XIVE);\n+ object_property_add_child(OBJECT(spapr), \"xive\", obj, &error_abort);\n+ object_property_add_const_link(obj, \"ics\", OBJECT(spapr->ics),\n+ &error_abort);\n+ object_property_set_int(obj, nr_irqs, \"nr-irqs\", &local_err);\n+ if (local_err) {\n+ goto error;\n+ }\n+ object_property_set_int(obj, nr_servers, \"nr-targets\", &local_err);\n+ if (local_err) {\n+ goto error;\n+ }\n+ object_property_set_bool(obj, true, \"realized\", &local_err);\n+ if (local_err) {\n+ goto error;\n+ }\n+\n+ return SPAPR_XIVE(obj);\n+error:\n+ error_propagate(errp, local_err);\n+ return NULL;\n+}\n+\n static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,\n int smt_threads)\n {\n@@ -1093,7 +1124,8 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr,\n }\n \n QLIST_FOREACH(phb, &spapr->phbs, list) {\n- ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt, XICS_IRQS_SPAPR);\n+ ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt,\n+ XICS_IRQS_SPAPR + xics_max_server_number());\n if (ret < 0) {\n error_report(\"couldn't setup PCI devices in fdt\");\n exit(1);\n@@ -2140,6 +2172,16 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)\n g_free(type);\n }\n \n+/*\n+ * Only POWER9 Processor chips support the XIVE interrupt controller\n+ */\n+static bool ppc_support_xive(MachineState *machine)\n+{\n+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(first_cpu);\n+\n+ return pcc->pvr_match(pcc, CPU_POWERPC_POWER9_BASE);\n+}\n+\n /* pSeries LPAR / sPAPR hardware init */\n static void ppc_spapr_init(MachineState *machine)\n {\n@@ -2237,7 +2279,8 @@ static void ppc_spapr_init(MachineState *machine)\n load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;\n \n /* Set up Interrupt Controller before we create the VCPUs */\n- xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);\n+ xics_system_init(machine, XICS_IRQS_SPAPR + xics_max_server_number(),\n+ &error_fatal);\n \n /* Set up containers for ibm,client-set-architecture negotiated options */\n spapr->ov5 = spapr_ovec_new();\n@@ -2274,6 +2317,22 @@ static void ppc_spapr_init(MachineState *machine)\n \n spapr_init_cpus(spapr);\n \n+ /* Set up XIVE. CAS will choose whether the guest runs in XICS\n+ * (legacy mode) or XIVE Exploitation mode\n+ *\n+ * We don't have KVM support yet, so check for irqchip=on\n+ */\n+ if (ppc_support_xive(machine)) {\n+ if (kvm_enabled() && machine_kernel_irqchip_required(machine)) {\n+ error_report(\"kernel_irqchip requested. no XIVE support\");\n+ } else {\n+ spapr->xive = spapr_spapr_xive_create(spapr,\n+ XICS_IRQS_SPAPR + xics_max_server_number(),\n+ xics_max_server_number(),\n+ &error_fatal);\n+ }\n+ }\n+\n if (kvm_enabled()) {\n /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */\n kvmppc_enable_logical_ci_hcalls();\ndiff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h\nindex 2a303a705c17..6cd5ab73c5dc 100644\n--- a/include/hw/ppc/spapr.h\n+++ b/include/hw/ppc/spapr.h\n@@ -14,6 +14,7 @@ struct sPAPRNVRAM;\n typedef struct sPAPREventLogEntry sPAPREventLogEntry;\n typedef struct sPAPREventSource sPAPREventSource;\n typedef struct sPAPRPendingHPT sPAPRPendingHPT;\n+typedef struct sPAPRXive sPAPRXive;\n \n #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL\n #define SPAPR_ENTRY_POINT 0x100\n@@ -127,6 +128,7 @@ struct sPAPRMachineState {\n MemoryHotplugState hotplug_memory;\n \n const char *icp_type;\n+ sPAPRXive *xive;\n };\n \n #define H_SUCCESS 0\n", "prefixes": [ "RFC", "v2", "16/21" ] }