[{"id":1770853,"web_url":"http://patchwork.ozlabs.org/comment/1770853/","msgid":"<20170919083818.GW27153@umbus>","list_archive_url":null,"date":"2017-09-19T08:38:18","subject":"Re: [Qemu-devel] [RFC PATCH v2 16/21] spapr: add a XIVE object to\n\tthe sPAPR machine","submitter":{"id":47,"url":"http://patchwork.ozlabs.org/api/people/47/","name":"David Gibson","email":"david@gibson.dropbear.id.au"},"content":"On Mon, Sep 11, 2017 at 07:12:30PM +0200, Cédric Le Goater wrote:\n> If the machine supports XIVE (POWER9 CPU), create a XIVE object. The\n> CAS negotiation process will decide which model (legacy or XIVE) will\n> be used for the interrupt controller depending on the guest\n> capabilities.\n> \n> Also extend the number of provisionned IRQs with the number of CPUs,\n> this is required for XIVE which allocates one IRQ number for each IPI.\n> \n> Signed-off-by: Cédric Le Goater \n> ---\n> hw/ppc/spapr.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++--\n> include/hw/ppc/spapr.h | 2 ++\n> 2 files changed, 63 insertions(+), 2 deletions(-)\n> \n> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c\n> index 5d69df928434..b6577dbecdea 100644\n> --- a/hw/ppc/spapr.c\n> +++ b/hw/ppc/spapr.c\n> @@ -44,6 +44,7 @@\n> #include \"mmu-hash64.h\"\n> #include \"mmu-book3s-v3.h\"\n> #include \"qom/cpu.h\"\n> +#include \"target/ppc/cpu-models.h\"\n> \n> #include \"hw/boards.h\"\n> #include \"hw/ppc/ppc.h\"\n> @@ -54,6 +55,7 @@\n> #include \"hw/ppc/spapr_vio.h\"\n> #include \"hw/pci-host/spapr.h\"\n> #include \"hw/ppc/xics.h\"\n> +#include \"hw/ppc/spapr_xive.h\"\n> #include \"hw/pci/msi.h\"\n> \n> #include \"hw/pci/pci.h\"\n> @@ -202,6 +204,35 @@ static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)\n> }\n> }\n> \n> +static sPAPRXive *spapr_spapr_xive_create(sPAPRMachineState *spapr, int nr_irqs,\n> + int nr_servers, Error **errp)\n> +{\n> + Error *local_err = NULL;\n> + Object *obj;\n> +\n> + obj = object_new(TYPE_SPAPR_XIVE);\n> + object_property_add_child(OBJECT(spapr), \"xive\", obj, &error_abort);\n> + object_property_add_const_link(obj, \"ics\", OBJECT(spapr->ics),\n> + &error_abort);\n> + object_property_set_int(obj, nr_irqs, \"nr-irqs\", &local_err);\n> + if (local_err) {\n> + goto error;\n> + }\n> + object_property_set_int(obj, nr_servers, \"nr-targets\", &local_err);\n> + if (local_err) {\n> + goto error;\n> + }\n> + object_property_set_bool(obj, true, \"realized\", &local_err);\n> + if (local_err) {\n> + goto error;\n> + }\n> +\n> + return SPAPR_XIVE(obj);\n> +error:\n> + error_propagate(errp, local_err);\n> + return NULL;\n> +}\n> +\n> static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,\n> int smt_threads)\n> {\n> @@ -1093,7 +1124,8 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr,\n> }\n> \n> QLIST_FOREACH(phb, &spapr->phbs, list) {\n> - ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt, XICS_IRQS_SPAPR);\n> + ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt,\n> + XICS_IRQS_SPAPR + xics_max_server_number());\n> if (ret < 0) {\n> error_report(\"couldn't setup PCI devices in fdt\");\n> exit(1);\n> @@ -2140,6 +2172,16 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)\n> g_free(type);\n> }\n> \n> +/*\n> + * Only POWER9 Processor chips support the XIVE interrupt controller\n> + */\n> +static bool ppc_support_xive(MachineState *machine)\n> +{\n> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(first_cpu);\n> +\n> + return pcc->pvr_match(pcc, CPU_POWERPC_POWER9_BASE);\n> +}\n> +\n> /* pSeries LPAR / sPAPR hardware init */\n> static void ppc_spapr_init(MachineState *machine)\n> {\n> @@ -2237,7 +2279,8 @@ static void ppc_spapr_init(MachineState *machine)\n> load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;\n> \n> /* Set up Interrupt Controller before we create the VCPUs */\n> - xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);\n> + xics_system_init(machine, XICS_IRQS_SPAPR + xics_max_server_number(),\n> + &error_fatal);\n\nHas this hunk leaked from another patch? AFAICT it only affects XICS\nwith what you have so far, which doesn't seem like what you want.\n\n> /* Set up containers for ibm,client-set-architecture negotiated options */\n> spapr->ov5 = spapr_ovec_new();\n> @@ -2274,6 +2317,22 @@ static void ppc_spapr_init(MachineState *machine)\n> \n> spapr_init_cpus(spapr);\n> \n> + /* Set up XIVE. CAS will choose whether the guest runs in XICS\n> + * (legacy mode) or XIVE Exploitation mode\n> + *\n> + * We don't have KVM support yet, so check for irqchip=on\n> + */\n> + if (ppc_support_xive(machine)) {\n> + if (kvm_enabled() && machine_kernel_irqchip_required(machine)) {\n> + error_report(\"kernel_irqchip requested. no XIVE support\");\n> + } else {\n> + spapr->xive = spapr_spapr_xive_create(spapr,\n> + XICS_IRQS_SPAPR + xics_max_server_number(),\n> + xics_max_server_number(),\n> + &error_fatal);\n> + }\n> + }\n> +\n> if (kvm_enabled()) {\n> /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */\n> kvmppc_enable_logical_ci_hcalls();\n> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h\n> index 2a303a705c17..6cd5ab73c5dc 100644\n> --- a/include/hw/ppc/spapr.h\n> +++ b/include/hw/ppc/spapr.h\n> @@ -14,6 +14,7 @@ struct sPAPRNVRAM;\n> typedef struct sPAPREventLogEntry sPAPREventLogEntry;\n> typedef struct sPAPREventSource sPAPREventSource;\n> typedef struct sPAPRPendingHPT sPAPRPendingHPT;\n> +typedef struct sPAPRXive sPAPRXive;\n> \n> #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL\n> #define SPAPR_ENTRY_POINT 0x100\n> @@ -127,6 +128,7 @@ struct sPAPRMachineState {\n> MemoryHotplugState hotplug_memory;\n> \n> const char *icp_type;\n> + sPAPRXive *xive;\n> };\n> \n> #define H_SUCCESS 0","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=gibson.dropbear.id.au\n\theader.i=@gibson.dropbear.id.au header.b=\"N40/HZCc\"; \n\tdkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxKQs6Hyxz9s7m\n\tfor ;\n\tTue, 19 Sep 2017 20:50:29 +1000 (AEST)","from localhost ([::1]:41419 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1duG6l-0003ln-VV\n\tfor incoming@patchwork.ozlabs.org; Tue, 19 Sep 2017 06:50:28 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:51366)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1duFtb-0001K1-HQ\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 06:36:54 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1duFtY-00030d-7M\n\tfor qemu-devel@nongnu.org; Tue, 19 Sep 2017 06:36:51 -0400","from ozlabs.org ([2401:3900:2:1::2]:57703)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1duFtX-0002tm-Ha; Tue, 19 Sep 2017 06:36:48 -0400","by ozlabs.org (Postfix, from userid 1007)\n\tid 3xxK6r0sGjz9t4X; Tue, 19 Sep 2017 20:36:34 +1000 (AEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n\td=gibson.dropbear.id.au; s=201602; t=1505817396;\n\tbh=hU30IBAOXYlWBQSrxaIW+DoEnlbz1cdmxpSg03/cWqM=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=N40/HZCcNoel8yrcEOPXPnXF5vayD2e8tHzvqbPtGVvGaz32oaRWxRG3lTlb6JSAz\n\tHjkavGU8xvgAQYCUfbPw1M0HQWqfpvtNi3/xbRdqyWN4SQIr3ukPQJ/aHcf7MDrzdl\n\tZlGaLmVJE2gwtpxd9RrZUpApC2qKUaaJCEXZwtb4=","Date":"Tue, 19 Sep 2017 18:38:18 +1000","From":"David Gibson ","To":"=?iso-8859-1?q?C=E9dric?= Le Goater ","Message-ID":"<20170919083818.GW27153@umbus>","References":"<20170911171235.29331-1-clg@kaod.org>\n\t<20170911171235.29331-17-clg@kaod.org>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"ngiTnHdmUEG79yp6\"","Content-Disposition":"inline","In-Reply-To":"<20170911171235.29331-17-clg@kaod.org>","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2401:3900:2:1::2","Subject":"Re: [Qemu-devel] [RFC PATCH v2 16/21] spapr: add a XIVE object to\n\tthe sPAPR machine","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alexey Kardashevskiy , qemu-ppc@nongnu.org,\n\tqemu-devel@nongnu.org, Alexander Graf ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1771868,"web_url":"http://patchwork.ozlabs.org/comment/1771868/","msgid":"<85b1f88f-77ff-8d3e-c710-b7273564637c@kaod.org>","list_archive_url":null,"date":"2017-09-20T09:51:56","subject":"Re: [Qemu-devel] [RFC PATCH v2 16/21] spapr: add a XIVE object to\n\tthe sPAPR machine","submitter":{"id":68548,"url":"http://patchwork.ozlabs.org/api/people/68548/","name":"Cédric Le Goater","email":"clg@kaod.org"},"content":"On 09/19/2017 10:38 AM, David Gibson wrote:\n> On Mon, Sep 11, 2017 at 07:12:30PM +0200, Cédric Le Goater wrote:\n>> If the machine supports XIVE (POWER9 CPU), create a XIVE object. The\n>> CAS negotiation process will decide which model (legacy or XIVE) will\n>> be used for the interrupt controller depending on the guest\n>> capabilities.\n>>\n>> Also extend the number of provisionned IRQs with the number of CPUs,\n>> this is required for XIVE which allocates one IRQ number for each IPI.\n>>\n>> Signed-off-by: Cédric Le Goater \n>> ---\n>> hw/ppc/spapr.c | 63 ++++++++++++++++++++++++++++++++++++++++++++++++--\n>> include/hw/ppc/spapr.h | 2 ++\n>> 2 files changed, 63 insertions(+), 2 deletions(-)\n>>\n>> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c\n>> index 5d69df928434..b6577dbecdea 100644\n>> --- a/hw/ppc/spapr.c\n>> +++ b/hw/ppc/spapr.c\n>> @@ -44,6 +44,7 @@\n>> #include \"mmu-hash64.h\"\n>> #include \"mmu-book3s-v3.h\"\n>> #include \"qom/cpu.h\"\n>> +#include \"target/ppc/cpu-models.h\"\n>> \n>> #include \"hw/boards.h\"\n>> #include \"hw/ppc/ppc.h\"\n>> @@ -54,6 +55,7 @@\n>> #include \"hw/ppc/spapr_vio.h\"\n>> #include \"hw/pci-host/spapr.h\"\n>> #include \"hw/ppc/xics.h\"\n>> +#include \"hw/ppc/spapr_xive.h\"\n>> #include \"hw/pci/msi.h\"\n>> \n>> #include \"hw/pci/pci.h\"\n>> @@ -202,6 +204,35 @@ static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp)\n>> }\n>> }\n>> \n>> +static sPAPRXive *spapr_spapr_xive_create(sPAPRMachineState *spapr, int nr_irqs,\n>> + int nr_servers, Error **errp)\n>> +{\n>> + Error *local_err = NULL;\n>> + Object *obj;\n>> +\n>> + obj = object_new(TYPE_SPAPR_XIVE);\n>> + object_property_add_child(OBJECT(spapr), \"xive\", obj, &error_abort);\n>> + object_property_add_const_link(obj, \"ics\", OBJECT(spapr->ics),\n>> + &error_abort);\n>> + object_property_set_int(obj, nr_irqs, \"nr-irqs\", &local_err);\n>> + if (local_err) {\n>> + goto error;\n>> + }\n>> + object_property_set_int(obj, nr_servers, \"nr-targets\", &local_err);\n>> + if (local_err) {\n>> + goto error;\n>> + }\n>> + object_property_set_bool(obj, true, \"realized\", &local_err);\n>> + if (local_err) {\n>> + goto error;\n>> + }\n>> +\n>> + return SPAPR_XIVE(obj);\n>> +error:\n>> + error_propagate(errp, local_err);\n>> + return NULL;\n>> +}\n>> +\n>> static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,\n>> int smt_threads)\n>> {\n>> @@ -1093,7 +1124,8 @@ static void *spapr_build_fdt(sPAPRMachineState *spapr,\n>> }\n>> \n>> QLIST_FOREACH(phb, &spapr->phbs, list) {\n>> - ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt, XICS_IRQS_SPAPR);\n>> + ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt,\n>> + XICS_IRQS_SPAPR + xics_max_server_number());\n>> if (ret < 0) {\n>> error_report(\"couldn't setup PCI devices in fdt\");\n>> exit(1);\n>> @@ -2140,6 +2172,16 @@ static void spapr_init_cpus(sPAPRMachineState *spapr)\n>> g_free(type);\n>> }\n>> \n>> +/*\n>> + * Only POWER9 Processor chips support the XIVE interrupt controller\n>> + */\n>> +static bool ppc_support_xive(MachineState *machine)\n>> +{\n>> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(first_cpu);\n>> +\n>> + return pcc->pvr_match(pcc, CPU_POWERPC_POWER9_BASE);\n>> +}\n>> +\n>> /* pSeries LPAR / sPAPR hardware init */\n>> static void ppc_spapr_init(MachineState *machine)\n>> {\n>> @@ -2237,7 +2279,8 @@ static void ppc_spapr_init(MachineState *machine)\n>> load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;\n>> \n>> /* Set up Interrupt Controller before we create the VCPUs */\n>> - xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal);\n>> + xics_system_init(machine, XICS_IRQS_SPAPR + xics_max_server_number(),\n>> + &error_fatal);\n> \n> Has this hunk leaked from another patch? AFAICT it only affects XICS\n> with what you have so far, which doesn't seem like what you want.\n\nno. We are sharing the ICSIRQState array of XICS. This is why.\n\nC. \n\n>> /* Set up containers for ibm,client-set-architecture negotiated options */\n>> spapr->ov5 = spapr_ovec_new();\n>> @@ -2274,6 +2317,22 @@ static void ppc_spapr_init(MachineState *machine)\n>> \n>> spapr_init_cpus(spapr);\n>> \n>> + /* Set up XIVE. CAS will choose whether the guest runs in XICS\n>> + * (legacy mode) or XIVE Exploitation mode\n>> + *\n>> + * We don't have KVM support yet, so check for irqchip=on\n>> + */\n>> + if (ppc_support_xive(machine)) {\n>> + if (kvm_enabled() && machine_kernel_irqchip_required(machine)) {\n>> + error_report(\"kernel_irqchip requested. no XIVE support\");\n>> + } else {\n>> + spapr->xive = spapr_spapr_xive_create(spapr,\n>> + XICS_IRQS_SPAPR + xics_max_server_number(),\n>> + xics_max_server_number(),\n>> + &error_fatal);\n>> + }\n>> + }\n>> +\n>> if (kvm_enabled()) {\n>> /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */\n>> kvmppc_enable_logical_ci_hcalls();\n>> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h\n>> index 2a303a705c17..6cd5ab73c5dc 100644\n>> --- a/include/hw/ppc/spapr.h\n>> +++ b/include/hw/ppc/spapr.h\n>> @@ -14,6 +14,7 @@ struct sPAPRNVRAM;\n>> typedef struct sPAPREventLogEntry sPAPREventLogEntry;\n>> typedef struct sPAPREventSource sPAPREventSource;\n>> typedef struct sPAPRPendingHPT sPAPRPendingHPT;\n>> +typedef struct sPAPRXive sPAPRXive;\n>> \n>> #define HPTE64_V_HPTE_DIRTY 0x0000000000000040ULL\n>> #define SPAPR_ENTRY_POINT 0x100\n>> @@ -127,6 +128,7 @@ struct sPAPRMachineState {\n>> MemoryHotplugState hotplug_memory;\n>> \n>> const char *icp_type;\n>> + sPAPRXive *xive;\n>> };\n>> \n>> #define H_SUCCESS 0\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xy1N02l52z9s7f\n\tfor ;\n\tWed, 20 Sep 2017 23:50:24 +1000 (AEST)","from localhost ([::1]:48196 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dufOQ-0005Hs-A5\n\tfor incoming@patchwork.ozlabs.org; Wed, 20 Sep 2017 09:50:22 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:38925)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1duf5m-0006Pj-Du\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 09:31:07 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1duf5i-0006u2-4O\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 09:31:06 -0400","from 5.mo2.mail-out.ovh.net ([87.98.181.248]:60490)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from ) id 1duf5h-0006tP-Qy\n\tfor qemu-devel@nongnu.org; Wed, 20 Sep 2017 09:31:02 -0400","from player157.ha.ovh.net (b9.ovh.net [213.186.33.59])\n\tby mo2.mail-out.ovh.net (Postfix) with ESMTP id B8CB4AC355\n\tfor ; Wed, 20 Sep 2017 11:52:01 +0200 (CEST)","from zorba.kaod.org (LFbn-1-2231-173.w90-76.abo.wanadoo.fr\n\t[90.76.52.173]) (Authenticated sender: postmaster@kaod.org)\n\tby player157.ha.ovh.net (Postfix) with ESMTPSA id 840005000A5;\n\tWed, 20 Sep 2017 11:51:56 +0200 (CEST)"],"To":"David Gibson ","References":"<20170911171235.29331-1-clg@kaod.org>\n\t<20170911171235.29331-17-clg@kaod.org> <20170919083818.GW27153@umbus>","From":"=?utf-8?q?C=C3=A9dric_Le_Goater?= ","Message-ID":"<85b1f88f-77ff-8d3e-c710-b7273564637c@kaod.org>","Date":"Wed, 20 Sep 2017 11:51:56 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170919083818.GW27153@umbus>","Content-Type":"text/plain; charset=windows-1252","Content-Language":"en-US","X-Ovh-Tracer-Id":"4197636327773539192","X-VR-SPAMSTATE":"OK","X-VR-SPAMSCORE":"-100","X-VR-SPAMCAUSE":"gggruggvucftvghtrhhoucdtuddrfeelledrheelgddvudcutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfqggfjpdevjffgvefmvefgnecuuegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmd","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"87.98.181.248","Subject":"Re: [Qemu-devel] [RFC PATCH v2 16/21] spapr: add a XIVE object to\n\tthe sPAPR machine","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Alexey Kardashevskiy , qemu-ppc@nongnu.org,\n\tqemu-devel@nongnu.org, Alexander Graf ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]