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GET /api/patches/812468/?format=api
{ "id": 812468, "url": "http://patchwork.ozlabs.org/api/patches/812468/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911171235.29331-13-clg@kaod.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170911171235.29331-13-clg@kaod.org>", "list_archive_url": null, "date": "2017-09-11T17:12:26", "name": "[RFC,v2,12/21] ppc/xive: notify the CPU when interrupt priority is more privileged", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "57751991b4f4853ab490420e4e3ba98d1d377452", "submitter": { "id": 68548, "url": "http://patchwork.ozlabs.org/api/people/68548/?format=api", "name": "Cédric Le Goater", "email": "clg@kaod.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170911171235.29331-13-clg@kaod.org/mbox/", "series": [ { "id": 2526, "url": "http://patchwork.ozlabs.org/api/series/2526/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2526", "date": "2017-09-11T17:12:14", "name": "Guest exploitation of the XIVE interrupt controller (POWER9)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2526/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/812468/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/812468/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xrZW96Vb0z9s81\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 12 Sep 2017 03:22:45 +1000 (AEST)", "from localhost ([::1]:59313 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1drSPz-000867-TE\n\tfor incoming@patchwork.ozlabs.org; Mon, 11 Sep 2017 13:22:43 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:35382)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <clg@kaod.org>) id 1drSHs-0001QQ-Uc\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:14:21 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <clg@kaod.org>) id 1drSHo-0004U8-Dx\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:14:20 -0400", "from 3.mo2.mail-out.ovh.net ([46.105.58.226]:59734)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from <clg@kaod.org>) id 1drSHo-0004Ti-88\n\tfor qemu-devel@nongnu.org; Mon, 11 Sep 2017 13:14:16 -0400", "from player770.ha.ovh.net (b6.ovh.net [213.186.33.56])\n\tby mo2.mail-out.ovh.net (Postfix) with ESMTP id 507E3AB262\n\tfor <qemu-devel@nongnu.org>; Mon, 11 Sep 2017 19:14:15 +0200 (CEST)", "from zorba.kaod.org.com (LFbn-1-2231-173.w90-76.abo.wanadoo.fr\n\t[90.76.52.173]) (Authenticated sender: clg@kaod.org)\n\tby player770.ha.ovh.net (Postfix) with ESMTPSA id 1C2663C0072;\n\tMon, 11 Sep 2017 19:14:08 +0200 (CEST)" ], "From": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "To": "qemu-ppc@nongnu.org, qemu-devel@nongnu.org,\n\tDavid Gibson <david@gibson.dropbear.id.au>,\n\tBenjamin Herrenschmidt <benh@kernel.crashing.org>,\n\tAlexey Kardashevskiy <aik@ozlabs.ru>, Alexander Graf <agraf@suse.de>", "Date": "Mon, 11 Sep 2017 19:12:26 +0200", "Message-Id": "<20170911171235.29331-13-clg@kaod.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170911171235.29331-1-clg@kaod.org>", "References": "<20170911171235.29331-1-clg@kaod.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "X-Ovh-Tracer-Id": "14152280358323194707", "X-VR-SPAMSTATE": "OK", "X-VR-SPAMSCORE": "-100", "X-VR-SPAMCAUSE": "gggruggvucftvghtrhhoucdtuddrfeelledrgedtgdduudehucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddm", "Content-Transfer-Encoding": "quoted-printable", "X-detected-operating-system": "by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]", "X-Received-From": "46.105.58.226", "Subject": "[Qemu-devel] [RFC PATCH v2 12/21] ppc/xive: notify the CPU when\n\tinterrupt priority is more privileged", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "=?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "The Pending Interrupt Priority Register (PIPR) contains the priority\nof the most favored pending notification. It is calculated from the\nInterrupt Pending Buffer (IPB) which indicates a pending interrupt at\nthe priority corresponding to the bit number.\n\nIf the PIPR is more favored (1) than the Current Processor Priority\nRegister (CPPR), the CPU interrupt line can be raised and the EO bit\nof the Notification Source Register is updated to notify the presence\nof an exception for the O/S. The check needs to be done whenever the\nPIPR or the CPPR is changed.\n\n(1) numerically less than\n\nSigned-off-by: Cédric Le Goater <clg@kaod.org>\n---\n hw/intc/spapr_xive.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 50 insertions(+)", "diff": "diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c\nindex 4bc61cfda67a..e5d4b723b7e0 100644\n--- a/hw/intc/spapr_xive.c\n+++ b/hw/intc/spapr_xive.c\n@@ -28,11 +28,39 @@\n #include \"xive-internal.h\"\n \n \n+/* Convert a priority number to an Interrupt Pending Buffer (IPB)\n+ * register, which indicates a pending interrupt at the priority\n+ * corresponding to the bit number\n+ */\n+static uint8_t priority_to_ipb(uint8_t priority)\n+{\n+ return priority > XIVE_PRIORITY_MAX ? 0 : 1 << (7 - priority);\n+}\n+\n+/* Convert an Interrupt Pending Buffer (IPB) register to a Pending\n+ * Interrupt Priority Register (PIPR), which contains the priority of\n+ * the most favored pending notification.\n+ *\n+ * TODO: PIPR can never be OxFF. Needs a fix.\n+ */\n+static uint8_t ipb_to_pipr(uint8_t ibp)\n+{\n+ return ibp ? clz32((uint32_t)ibp << 24) : 0xff;\n+}\n+\n static uint64_t spapr_xive_icp_accept(ICPState *icp)\n {\n return 0;\n }\n \n+static void spapr_xive_icp_notify(ICPState *icp)\n+{\n+ if (icp->tima_os[TM_PIPR] < icp->tima_os[TM_CPPR]) {\n+ icp->tima_os[TM_NSR] |= TM_QW1_NSR_EO;\n+ qemu_irq_raise(ICP(icp)->output);\n+ }\n+}\n+\n static void spapr_xive_icp_set_cppr(ICPState *icp, uint8_t cppr)\n {\n if (cppr > XIVE_PRIORITY_MAX) {\n@@ -40,6 +68,10 @@ static void spapr_xive_icp_set_cppr(ICPState *icp, uint8_t cppr)\n }\n \n icp->tima_os[TM_CPPR] = cppr;\n+\n+ /* CPPR has changed, inform the ICP which might raise an\n+ * exception */\n+ spapr_xive_icp_notify(icp);\n }\n \n /*\n@@ -206,6 +238,8 @@ static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n XiveEQ *eq;\n uint32_t eq_idx;\n uint32_t priority;\n+ uint32_t target;\n+ ICPState *icp;\n \n ive = spapr_xive_get_ive(xive, srcno);\n if (!ive || !(ive->w & IVE_VALID)) {\n@@ -235,6 +269,13 @@ static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n qemu_log_mask(LOG_UNIMP, \"XIVE: !UCOND_NOTIFY not implemented\\n\");\n }\n \n+ target = GETFIELD(EQ_W6_NVT_INDEX, eq->w6);\n+ icp = xics_icp_get(xive->ics->xics, target);\n+ if (!icp) {\n+ qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: No ICP for target %d\\n\", target);\n+ return;\n+ }\n+\n if (GETFIELD(EQ_W6_FORMAT_BIT, eq->w6) == 0) {\n priority = GETFIELD(EQ_W7_F0_PRIORITY, eq->w7);\n \n@@ -242,9 +283,18 @@ static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n if (priority == 0xff) {\n return;\n }\n+\n+ /* Update the IPB (Interrupt Pending Buffer) with the priority\n+ * of the new notification and inform the ICP, which will\n+ * decide to raise the exception, or not, depending the CPPR.\n+ */\n+ icp->tima_os[TM_IPB] |= priority_to_ipb(priority);\n+ icp->tima_os[TM_PIPR] = ipb_to_pipr(icp->tima_os[TM_IPB]);\n } else {\n qemu_log_mask(LOG_UNIMP, \"XIVE: w7 format1 not implemented\\n\");\n }\n+\n+ spapr_xive_icp_notify(icp);\n }\n \n /*\n", "prefixes": [ "RFC", "v2", "12/21" ] }