[{"id":1770858,"web_url":"http://patchwork.ozlabs.org/comment/1770858/","msgid":"<20170919075008.GP27153@umbus>","list_archive_url":null,"date":"2017-09-19T07:50:08","subject":"Re: [Qemu-devel] [RFC PATCH v2 12/21] ppc/xive: notify the CPU when\n\tinterrupt priority is more privileged","submitter":{"id":47,"url":"http://patchwork.ozlabs.org/api/people/47/","name":"David Gibson","email":"david@gibson.dropbear.id.au"},"content":"On Mon, Sep 11, 2017 at 07:12:26PM +0200, Cédric Le Goater wrote:\n> The Pending Interrupt Priority Register (PIPR) contains the priority\n> of the most favored pending notification. It is calculated from the\n> Interrupt Pending Buffer (IPB) which indicates a pending interrupt at\n> the priority corresponding to the bit number.\n> \n> If the PIPR is more favored (1) than the Current Processor Priority\n> Register (CPPR), the CPU interrupt line can be raised and the EO bit\n> of the Notification Source Register is updated to notify the presence\n> of an exception for the O/S. The check needs to be done whenever the\n> PIPR or the CPPR is changed.\n> \n> (1) numerically less than\n> \n> Signed-off-by: Cédric Le Goater \n> ---\n> hw/intc/spapr_xive.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++\n> 1 file changed, 50 insertions(+)\n> \n> diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c\n> index 4bc61cfda67a..e5d4b723b7e0 100644\n> --- a/hw/intc/spapr_xive.c\n> +++ b/hw/intc/spapr_xive.c\n> @@ -28,11 +28,39 @@\n> #include \"xive-internal.h\"\n> \n> \n> +/* Convert a priority number to an Interrupt Pending Buffer (IPB)\n> + * register, which indicates a pending interrupt at the priority\n> + * corresponding to the bit number\n> + */\n> +static uint8_t priority_to_ipb(uint8_t priority)\n> +{\n> + return priority > XIVE_PRIORITY_MAX ? 0 : 1 << (7 - priority);\n> +}\n> +\n> +/* Convert an Interrupt Pending Buffer (IPB) register to a Pending\n> + * Interrupt Priority Register (PIPR), which contains the priority of\n> + * the most favored pending notification.\n> + *\n> + * TODO: PIPR can never be OxFF. Needs a fix.\n> + */\n> +static uint8_t ipb_to_pipr(uint8_t ibp)\n> +{\n> + return ibp ? clz32((uint32_t)ibp << 24) : 0xff;\n> +}\n> +\n> static uint64_t spapr_xive_icp_accept(ICPState *icp)\n> {\n> return 0;\n> }\n> \n> +static void spapr_xive_icp_notify(ICPState *icp)\n> +{\n> + if (icp->tima_os[TM_PIPR] < icp->tima_os[TM_CPPR]) {\n> + icp->tima_os[TM_NSR] |= TM_QW1_NSR_EO;\n> + qemu_irq_raise(ICP(icp)->output);\n\nThe CPU interrupt lines are effectively level sensitive, but you never\nlower this, AFAICT.\n\n> + }\n> +}\n> +\n> static void spapr_xive_icp_set_cppr(ICPState *icp, uint8_t cppr)\n> {\n> if (cppr > XIVE_PRIORITY_MAX) {\n> @@ -40,6 +68,10 @@ static void spapr_xive_icp_set_cppr(ICPState *icp, uint8_t cppr)\n> }\n> \n> icp->tima_os[TM_CPPR] = cppr;\n> +\n> + /* CPPR has changed, inform the ICP which might raise an\n> + * exception */\n> + spapr_xive_icp_notify(icp);\n> }\n> \n> /*\n> @@ -206,6 +238,8 @@ static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n> XiveEQ *eq;\n> uint32_t eq_idx;\n> uint32_t priority;\n> + uint32_t target;\n> + ICPState *icp;\n> \n> ive = spapr_xive_get_ive(xive, srcno);\n> if (!ive || !(ive->w & IVE_VALID)) {\n> @@ -235,6 +269,13 @@ static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n> qemu_log_mask(LOG_UNIMP, \"XIVE: !UCOND_NOTIFY not implemented\\n\");\n> }\n> \n> + target = GETFIELD(EQ_W6_NVT_INDEX, eq->w6);\n> + icp = xics_icp_get(xive->ics->xics, target);\n> + if (!icp) {\n> + qemu_log_mask(LOG_GUEST_ERROR, \"XIVE: No ICP for target %d\\n\", target);\n> + return;\n> + }\n> +\n> if (GETFIELD(EQ_W6_FORMAT_BIT, eq->w6) == 0) {\n> priority = GETFIELD(EQ_W7_F0_PRIORITY, eq->w7);\n> \n> @@ -242,9 +283,18 @@ static void spapr_xive_irq(sPAPRXive *xive, int srcno)\n> if (priority == 0xff) {\n> return;\n> }\n> +\n> + /* Update the IPB (Interrupt Pending Buffer) with the priority\n> + * of the new notification and inform the ICP, which will\n> + * decide to raise the exception, or not, depending the CPPR.\n> + */\n> + icp->tima_os[TM_IPB] |= priority_to_ipb(priority);\n> + icp->tima_os[TM_PIPR] = ipb_to_pipr(icp->tima_os[TM_IPB]);\n> } else {\n> qemu_log_mask(LOG_UNIMP, \"XIVE: w7 format1 not implemented\\n\");\n> }\n> +\n> + spapr_xive_icp_notify(icp);\n> }\n> \n> /*","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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