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GET /api/patches/811857/?format=api
{ "id": 811857, "url": "http://patchwork.ozlabs.org/api/patches/811857/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504910713-7094-2-git-send-email-linuxram@us.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1504910713-7094-2-git-send-email-linuxram@us.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1504910713-7094-2-git-send-email-linuxram@us.ibm.com/", "date": "2017-09-08T22:44:41", "name": "[1/7] powerpc: introduce pte_set_hash_slot() helper", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "e6290adeedb281e75ff72b9d90ffc16912d31358", "submitter": { "id": 2667, "url": "http://patchwork.ozlabs.org/api/people/2667/?format=api", "name": "Ram Pai", "email": "linuxram@us.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504910713-7094-2-git-send-email-linuxram@us.ibm.com/mbox/", "series": [ { "id": 2303, "url": "http://patchwork.ozlabs.org/api/series/2303/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=2303", "date": "2017-09-08T22:44:40", "name": "powerpc: Free up RPAGE_RSV bits", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/2303/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/811857/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/811857/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xpsvz43XLz9s8J\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Sep 2017 08:49:51 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xpsvz2sTwzDrck\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Sep 2017 08:49:51 +1000 (AEST)", "from mail-qt0-x243.google.com (mail-qt0-x243.google.com\n\t[IPv6:2607:f8b0:400d:c0d::243])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xpsr6691DzDrWB\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tSat, 9 Sep 2017 08:46:30 +1000 (AEST)", "by mail-qt0-x243.google.com with SMTP id h21so2357752qth.4\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tFri, 08 Sep 2017 15:46:30 -0700 (PDT)", "from localhost.localdomain (50-39-103-96.bvtn.or.frontiernet.net.\n\t[50.39.103.96]) by smtp.gmail.com with ESMTPSA id\n\tx124sm2033726qka.85.2017.09.08.15.46.26\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 08 Sep 2017 15:46:28 -0700 (PDT)" ], "Authentication-Results": [ "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"BMsYwhoO\"; dkim-atps=neutral", "lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"BMsYwhoO\"; dkim-atps=neutral", "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gmail.com\n\t(client-ip=2607:f8b0:400d:c0d::243; helo=mail-qt0-x243.google.com;\n\tenvelope-from=ram.n.pai@gmail.com; receiver=<UNKNOWN>)", "lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"BMsYwhoO\"; dkim-atps=neutral" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=8bltCl1xxktlTaq+oxRDe6QTln7zOLHT/mfkZV59ZP0=;\n\tb=BMsYwhoORmHUzHoCXp2/blKZoNPvvRJHdFZE5riEyv0J0PcMN7PP4aUyGLrNWYKb4b\n\tl9Jej2GkAyPTGqvlVF1XHazPBiOL/1Lw8hUFNOX0igGtDlxnilOfITpU2EScOICcWut/\n\t+lg7PZIP4PdM3L928HZRAE5g0ljPSiUXvaz0FMLGORoMuEH5gaTJKraGejNRsRG8wFOs\n\tbht3xF6wUfl8lZabRE1hRHXLBuzPvglxdnNq3TnnQESVDmNIf4/E/ZtPwx1/Z1MXZMoD\n\t9P6YRqkMlGxltemxz3LIkkF5Hbj7+1/yuEETiw52FynWK1zxebTL4th18BUd8lxlYeIG\n\tckew==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references;\n\tbh=8bltCl1xxktlTaq+oxRDe6QTln7zOLHT/mfkZV59ZP0=;\n\tb=oV3gBL4SEv5t8hNCSFtUBKTdTyCfghPhTnk8XlZOnGV0xpwhgi6citi9Eiu/ZKrCFf\n\t/FbbCPnUYdhaLY7cnVLSwJIcUmGNAXnSiMkQHhDaPPeWU8cctLo9XDF8vSBDFTEwTozV\n\tg2Co0fDQMZMeJSS5eToNWM93glr/AWmfudGWpTIywvNPETxZWtfPQXI6PF7AMj4gJ12c\n\taYrT+V4Ga6p+/rYp9zl6HNvJS9KXTMmneAsDIbFnzGi6oCeIgjVTcWcyuymAmepYfxge\n\tx29XzgujH+ZKN1bkSnAIIl36XgoPs3AJhPN54L3d75GpYku9NSSq+GHWZeXuzrawQeAl\n\t/xAQ==", "X-Gm-Message-State": "AHPjjUgVu6hXhp4NVVW2a17xXiwkTtyXEZNzAmx5Nr3j/r0HoKAQ6DOF\n\t30a4zxquHMvpRw==", "X-Google-Smtp-Source": "AOwi7QCKrVfz9jeQeev3SWShAzK/f+yTZY+0PjhK2JYrORYtQ/GUeIPkCBBg1Dpsl9MmoFcHSvowgw==", "X-Received": "by 10.237.59.221 with SMTP id s29mr6655673qte.27.1504910788650; \n\tFri, 08 Sep 2017 15:46:28 -0700 (PDT)", "From": "Ram Pai <linuxram@us.ibm.com>", "To": "mpe@ellerman.id.au,\n\tlinuxppc-dev@lists.ozlabs.org", "Subject": "[PATCH 1/7] powerpc: introduce pte_set_hash_slot() helper", "Date": "Fri, 8 Sep 2017 15:44:41 -0700", "Message-Id": "<1504910713-7094-2-git-send-email-linuxram@us.ibm.com>", "X-Mailer": "git-send-email 1.7.1", "In-Reply-To": "<1504910713-7094-1-git-send-email-linuxram@us.ibm.com>", "References": "<1504910713-7094-1-git-send-email-linuxram@us.ibm.com>", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "ebiederm@xmission.com, linuxram@us.ibm.com, mhocko@kernel.org,\n\tpaulus@samba.org, aneesh.kumar@linux.vnet.ibm.com,\n\tbauerman@linux.vnet.ibm.com, khandual@linux.vnet.ibm.com", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Introduce pte_set_hash_slot().It sets the (H_PAGE_F_SECOND|H_PAGE_F_GIX)\nbits at the appropriate location in the PTE of 4K PTE. For\n64K PTE, it sets the bits in the second part of the PTE. Though\nthe implementation for the former just needs the slot parameter, it does\ntake some additional parameters to keep the prototype consistent.\n\nThis function will be handy as we work towards re-arranging the\nbits in the later patches.\n\nReviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>\nSigned-off-by: Ram Pai <linuxram@us.ibm.com>\n---\n arch/powerpc/include/asm/book3s/64/hash-4k.h | 15 +++++++++++++++\n arch/powerpc/include/asm/book3s/64/hash-64k.h | 25 +++++++++++++++++++++++++\n 2 files changed, 40 insertions(+), 0 deletions(-)", "diff": "diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h\nindex 0c4e470..8909039 100644\n--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h\n+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h\n@@ -48,6 +48,21 @@ static inline int hash__hugepd_ok(hugepd_t hpd)\n }\n #endif\n \n+/*\n+ * 4k pte format is different from 64k pte format. Saving the\n+ * hash_slot is just a matter of returning the pte bits that need to\n+ * be modified. On 64k pte, things are a little more involved and\n+ * hence needs many more parameters to accomplish the same.\n+ * However we want to abstract this out from the caller by keeping\n+ * the prototype consistent across the two formats.\n+ */\n+static inline unsigned long pte_set_hash_slot(pte_t *ptep, real_pte_t rpte,\n+\t\t\tunsigned int subpg_index, unsigned long slot)\n+{\n+\treturn (slot << H_PAGE_F_GIX_SHIFT) &\n+\t\t(H_PAGE_F_SECOND | H_PAGE_F_GIX);\n+}\n+\n #ifdef CONFIG_TRANSPARENT_HUGEPAGE\n \n static inline char *get_hpte_slot_array(pmd_t *pmdp)\ndiff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h\nindex 9732837..6652669 100644\n--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h\n+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h\n@@ -74,6 +74,31 @@ static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)\n \treturn (pte_val(rpte.pte) >> H_PAGE_F_GIX_SHIFT) & 0xf;\n }\n \n+/*\n+ * Commit the hash slot and return pte bits that needs to be modified.\n+ * The caller is expected to modify the pte bits accordingly and\n+ * commit the pte to memory.\n+ */\n+static inline unsigned long pte_set_hash_slot(pte_t *ptep, real_pte_t rpte,\n+\t\tunsigned int subpg_index, unsigned long slot)\n+{\n+\tunsigned long *hidxp = (unsigned long *)(ptep + PTRS_PER_PTE);\n+\n+\trpte.hidx &= ~(0xfUL << (subpg_index << 2));\n+\t*hidxp = rpte.hidx | (slot << (subpg_index << 2));\n+\t/*\n+\t * Commit the hidx bits to memory before returning.\n+\t * Anyone reading pte must ensure hidx bits are\n+\t * read only after reading the pte by using the\n+\t * read-side barrier smp_rmb(). __real_pte() can\n+\t * help ensure that.\n+\t */\n+\tsmp_wmb();\n+\n+\t/* no pte bits to be modified, return 0x0UL */\n+\treturn 0x0UL;\n+}\n+\n #define __rpte_to_pte(r)\t((r).pte)\n extern bool __rpte_sub_valid(real_pte_t rpte, unsigned long index);\n /*\n", "prefixes": [ "1/7" ] }