[{"id":1767652,"web_url":"http://patchwork.ozlabs.org/comment/1767652/","msgid":"","date":"2017-09-13T07:55:53","subject":"Re: [PATCH 1/7] powerpc: introduce pte_set_hash_slot() helper","submitter":{"id":9347,"url":"http://patchwork.ozlabs.org/api/people/9347/","name":"Balbir Singh","email":"bsingharora@gmail.com"},"content":"On Sat, Sep 9, 2017 at 8:44 AM, Ram Pai wrote:\n> Introduce pte_set_hash_slot().It sets the (H_PAGE_F_SECOND|H_PAGE_F_GIX)\n> bits at the appropriate location in the PTE of 4K PTE. For\n> 64K PTE, it sets the bits in the second part of the PTE. Though\n> the implementation for the former just needs the slot parameter, it does\n> take some additional parameters to keep the prototype consistent.\n>\n> This function will be handy as we work towards re-arranging the\n> bits in the later patches.\n>\n> Reviewed-by: Aneesh Kumar K.V \n> Signed-off-by: Ram Pai \n> ---\n> arch/powerpc/include/asm/book3s/64/hash-4k.h | 15 +++++++++++++++\n> arch/powerpc/include/asm/book3s/64/hash-64k.h | 25 +++++++++++++++++++++++++\n> 2 files changed, 40 insertions(+), 0 deletions(-)\n>\n> diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h\n> index 0c4e470..8909039 100644\n> --- a/arch/powerpc/include/asm/book3s/64/hash-4k.h\n> +++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h\n> @@ -48,6 +48,21 @@ static inline int hash__hugepd_ok(hugepd_t hpd)\n> }\n> #endif\n>\n> +/*\n> + * 4k pte format is different from 64k pte format. Saving the\n> + * hash_slot is just a matter of returning the pte bits that need to\n> + * be modified. On 64k pte, things are a little more involved and\n> + * hence needs many more parameters to accomplish the same.\n> + * However we want to abstract this out from the caller by keeping\n> + * the prototype consistent across the two formats.\n> + */\n> +static inline unsigned long pte_set_hash_slot(pte_t *ptep, real_pte_t rpte,\n> + unsigned int subpg_index, unsigned long slot)\n> +{\n> + return (slot << H_PAGE_F_GIX_SHIFT) &\n> + (H_PAGE_F_SECOND | H_PAGE_F_GIX);\n> +}\n> +\n> #ifdef CONFIG_TRANSPARENT_HUGEPAGE\n>\n> static inline char *get_hpte_slot_array(pmd_t *pmdp)\n> diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h\n> index 9732837..6652669 100644\n> --- a/arch/powerpc/include/asm/book3s/64/hash-64k.h\n> +++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h\n> @@ -74,6 +74,31 @@ static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)\n> return (pte_val(rpte.pte) >> H_PAGE_F_GIX_SHIFT) & 0xf;\n> }\n>\n> +/*\n> + * Commit the hash slot and return pte bits that needs to be modified.\n> + * The caller is expected to modify the pte bits accordingly and\n> + * commit the pte to memory.\n> + */\n> +static inline unsigned long pte_set_hash_slot(pte_t *ptep, real_pte_t rpte,\n> + unsigned int subpg_index, unsigned long slot)\n> +{\n> + unsigned long *hidxp = (unsigned long *)(ptep + PTRS_PER_PTE);\n> +\n> + rpte.hidx &= ~(0xfUL << (subpg_index << 2));\n> + *hidxp = rpte.hidx | (slot << (subpg_index << 2));\n> + /*\n> + * Commit the hidx bits to memory before returning.\n> + * Anyone reading pte must ensure hidx bits are\n> + * read only after reading the pte by using the\n\nCan you lose the only and make it \"read after reading the pte\"\nread only is easy to confuse as read-only\n\n> + * read-side barrier smp_rmb(). __real_pte() can\n> + * help ensure that.\n> + */\n> + smp_wmb();\n> +\n> + /* no pte bits to be modified, return 0x0UL */\n> + return 0x0UL;\n\nAcked-by: Balbir Singh \n\nBalbir Singh.","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xsYtj63HLz9sNr\n\tfor ;\n\tWed, 13 Sep 2017 17:58:05 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xsYtj4wc7zDrL4\n\tfor ;\n\tWed, 13 Sep 2017 17:58:05 +1000 (AEST)","from mail-vk0-x242.google.com (mail-vk0-x242.google.com\n\t[IPv6:2607:f8b0:400c:c05::242])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xsYrF1NyFzDr2L\n\tfor ;\n\tWed, 13 Sep 2017 17:55:56 +1000 (AEST)","by mail-vk0-x242.google.com with SMTP id j189so3295880vka.0\n\tfor ;\n\tWed, 13 Sep 2017 00:55:56 -0700 (PDT)","by 10.176.75.25 with HTTP; Wed, 13 Sep 2017 00:55:53 -0700 (PDT)"],"Authentication-Results":["ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"j589qArB\"; dkim-atps=neutral","lists.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"j589qArB\"; dkim-atps=neutral","ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gmail.com\n\t(client-ip=2607:f8b0:400c:c05::242; helo=mail-vk0-x242.google.com;\n\tenvelope-from=bsingharora@gmail.com; receiver=)","lists.ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"j589qArB\"; dkim-atps=neutral"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=vEYtrEBnAzcjlhosPKFyylQAUCWfAPIRWRBX52SSsek=;\n\tb=j589qArBQpmUZDv2i9kVTF0aGtGsyrtCdPeBcvNxIpne4XKfAdDnYW3zF8Qsm3rFPq\n\tU5w/3Voa9aTr6V5feWlfJ9B9QCPqQXmqyZij6e2pZuTYNIYmIb503wSxaiFJcJ/G5/ZB\n\tDkU5yy/zu965WTgtNXRTUxBLDFMOoY4bO8DPak1YAcNdRdng4fjLQYqHgl0Xwt+Dlnpv\n\ti+/J/wSAZZrs9nxP1sjCIapuXgg/6qqL7qGAhjsk2BiOTYus8GB4jTZD+c5cacnC8btr\n\tDWSWbtTDMBe8N8eA47FdlUqOW6S7hoTS/U7QtsIKcdRdZz4X/ptevg5ux4s8A9wbBuZa\n\tSzdw==","X-Google-DKIM-Signature":"v=1; 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charset=\"UTF-8\"","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"Eric W. Biederman\" ,\n\tMichal Hocko , Paul Mackerras , \n\tAneesh Kumar KV ,\n\tThiago Jung Bauermann ,\n\t\"open list:LINUX FOR POWERPC \\(32-BIT AND 64-BIT\\)\"\n\t,\n\tAnshuman Khandual ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1790115,"web_url":"http://patchwork.ozlabs.org/comment/1790115/","msgid":"<87k1zrkad0.fsf@concordia.ellerman.id.au>","date":"2017-10-19T04:52:27","subject":"Re: [PATCH 1/7] powerpc: introduce pte_set_hash_slot() helper","submitter":{"id":46580,"url":"http://patchwork.ozlabs.org/api/people/46580/","name":"Michael Ellerman","email":"mpe@ellerman.id.au"},"content":"Ram Pai writes:\n> diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h\n> index 9732837..6652669 100644\n> --- a/arch/powerpc/include/asm/book3s/64/hash-64k.h\n> +++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h\n> @@ -74,6 +74,31 @@ static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)\n> \treturn (pte_val(rpte.pte) >> H_PAGE_F_GIX_SHIFT) & 0xf;\n> }\n> \n> +/*\n> + * Commit the hash slot and return pte bits that needs to be modified.\n> + * The caller is expected to modify the pte bits accordingly and\n> + * commit the pte to memory.\n> + */\n> +static inline unsigned long pte_set_hash_slot(pte_t *ptep, real_pte_t rpte,\n> +\t\tunsigned int subpg_index, unsigned long slot)\n> +{\n> +\tunsigned long *hidxp = (unsigned long *)(ptep + PTRS_PER_PTE);\n> +\n> +\trpte.hidx &= ~(0xfUL << (subpg_index << 2));\n> +\t*hidxp = rpte.hidx | (slot << (subpg_index << 2));\n ^\n stray space here\n> +\t/*\n> +\t * Commit the hidx bits to memory before returning.\n\nI'd prefer we didn't use \"commit\", it implies the bits are actually\nwritten to memory by the barrier, which is not true. The barrier is just\na barrier or fence which prevents some reorderings of the things before\nit and the things after it.\n\n> +\t * Anyone reading pte must ensure hidx bits are\n> +\t * read only after reading the pte by using the\n> +\t * read-side barrier smp_rmb().\n\nThat seems OK. Though I'm reminded that I dislike your justified\ncomments, the odd spacing is jarring to read.\n\n> __real_pte() can\n> +\t * help ensure that.\n\nIt doesn't help, it *does* do that.\n\ncheers","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yHc9F1wlYz9tXC\n\tfor ;\n\tThu, 19 Oct 2017 15:57:05 +1100 (AEDT)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3yHc9F188LzDrR0\n\tfor ;\n\tThu, 19 Oct 2017 15:57:05 +1100 (AEDT)","from ozlabs.org (ozlabs.org [IPv6:2401:3900:2:1::2])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3yHc3w3y2bzDqBr\n\tfor ;\n\tThu, 19 Oct 2017 15:52:28 +1100 (AEDT)","from authenticated.ozlabs.org (localhost [127.0.0.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPSA id 3yHc3v5trmz9tXF;\n\tThu, 19 Oct 2017 15:52:27 +1100 (AEDT)"],"From":"Michael Ellerman ","To":"Ram Pai , linuxppc-dev@lists.ozlabs.org","Subject":"Re: [PATCH 1/7] powerpc: introduce pte_set_hash_slot() helper","In-Reply-To":"<1504910713-7094-2-git-send-email-linuxram@us.ibm.com>","References":"<1504910713-7094-1-git-send-email-linuxram@us.ibm.com>\n\t<1504910713-7094-2-git-send-email-linuxram@us.ibm.com>","Date":"Thu, 19 Oct 2017 15:52:27 +1100","Message-ID":"<87k1zrkad0.fsf@concordia.ellerman.id.au>","MIME-Version":"1.0","Content-Type":"text/plain","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.24","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"ebiederm@xmission.com, linuxram@us.ibm.com, mhocko@kernel.org,\n\tpaulus@samba.org, aneesh.kumar@linux.vnet.ibm.com,\n\tbauerman@linux.vnet.ibm.com, khandual@linux.vnet.ibm.com","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}}]