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{
    "id": 811563,
    "url": "http://patchwork.ozlabs.org/api/patches/811563/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/1504873388-29195-2-git-send-email-vjonnal@xilinx.com/",
    "project": {
        "id": 28,
        "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api",
        "name": "Linux PCI development",
        "link_name": "linux-pci",
        "list_id": "linux-pci.vger.kernel.org",
        "list_email": "linux-pci@vger.kernel.org",
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    "msgid": "<1504873388-29195-2-git-send-email-vjonnal@xilinx.com>",
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    "date": "2017-09-08T12:23:03",
    "name": "[v2,1/5] PCI:xilinx-nwl: Enable Root DMA",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": false,
    "hash": "d17a8b24baab65e0546f5030288217741964bf37",
    "submitter": {
        "id": 72127,
        "url": "http://patchwork.ozlabs.org/api/people/72127/?format=api",
        "name": "Ravi Shankar Jonnalagadda",
        "email": "venkata.ravi.jonnalagadda@xilinx.com"
    },
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    "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/1504873388-29195-2-git-send-email-vjonnal@xilinx.com/mbox/",
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            "id": 2190,
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            "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=2190",
            "date": "2017-09-08T12:23:04",
            "name": "dmaengine: ZynqMP PS PCIe DMA driver",
            "version": 2,
            "mbox": "http://patchwork.ozlabs.org/series/2190/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/811563/comments/",
    "check": "pending",
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    "tags": {},
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        "From": "Ravi Shankar Jonnalagadda <venkata.ravi.jonnalagadda@xilinx.com>",
        "To": "<vinod.koul@intel.com>, <robh+dt@kernel.org>,\n\t<mark.rutland@arm.com>, <michal.simek@xilinx.com>,\n\t<soren.brinkmann@xilinx.com>, <dan.j.williams@intel.com>,\n\t<bhelgaas@google.com>, <vjonnal@xilinx.com>,\n\t<lorenzo.pieralisi@arm.com>, <bharat.kumar.gogada@xilinx.com>,\n\t<dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>,\n\t<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<rgummal@xilinx.com>",
        "Subject": "[PATCH v2 1/5] PCI:xilinx-nwl: Enable Root DMA",
        "Date": "Fri, 8 Sep 2017 17:53:03 +0530",
        "Message-ID": "<1504873388-29195-2-git-send-email-vjonnal@xilinx.com>",
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    },
    "content": "Enabling Root DMA interrupts\n\nAdding Root DMA translations to bridge for Register Access\n\nSigned-off-by: Ravi Shankar Jonnalagadda <vjonnal@xilinx.com>\nSigned-off-by: RaviKiran Gummaluri <rgummal@xilinx.com>\n---\n drivers/pci/host/pcie-xilinx-nwl.c | 15 +++++++++++++++\n 1 file changed, 15 insertions(+)",
    "diff": "diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c\nindex eec641a..5766582 100644\n--- a/drivers/pci/host/pcie-xilinx-nwl.c\n+++ b/drivers/pci/host/pcie-xilinx-nwl.c\n@@ -39,6 +39,11 @@\n #define E_ECAM_CONTROL\t\t\t0x00000228\n #define E_ECAM_BASE_LO\t\t\t0x00000230\n #define E_ECAM_BASE_HI\t\t\t0x00000234\n+#define E_DREG_CTRL\t\t\t0x00000288\n+#define E_DREG_BASE_LO\t\t\t0x00000290\n+\n+#define DREG_DMA_EN\t\t\tBIT(0)\n+#define DREG_DMA_BASE_LO\t\t0xFD0F0000\n \n /* Ingress - address translations */\n #define I_MSII_CAPABILITIES\t\t0x00000300\n@@ -57,6 +62,10 @@\n #define MSGF_MSI_STATUS_HI\t\t0x00000444\n #define MSGF_MSI_MASK_LO\t\t0x00000448\n #define MSGF_MSI_MASK_HI\t\t0x0000044C\n+/* Root DMA Interrupt register */\n+#define MSGF_DMA_MASK\t\t\t0x00000464\n+\n+#define MSGF_INTR_EN\t\t\tBIT(0)\n \n /* Msg filter mask bits */\n #define CFG_ENABLE_PM_MSG_FWD\t\tBIT(1)\n@@ -766,6 +775,12 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)\n \tnwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &\n \t\t\t  MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);\n \n+\t/* Enabling DREG translations */\n+\tnwl_bridge_writel(pcie, DREG_DMA_EN, E_DREG_CTRL);\n+\tnwl_bridge_writel(pcie, DREG_DMA_BASE_LO, E_DREG_BASE_LO);\n+\t/* Enabling Root DMA interrupts */\n+\tnwl_bridge_writel(pcie, MSGF_INTR_EN, MSGF_DMA_MASK);\n+\n \t/* Enable all legacy interrupts */\n \tnwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);\n \n",
    "prefixes": [
        "v2",
        "1/5"
    ]
}