[{"id":1771319,"web_url":"http://patchwork.ozlabs.org/comment/1771319/","msgid":"<20170919193635.GE22312@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-09-19T19:36:35","subject":"Re: [PATCH v2 1/5] PCI:xilinx-nwl: Enable Root DMA","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"Hi Ravi,\n\nPlease make the subject line follow the existing convention, i.e., run\n\n $ git log --oneline drivers/pci/host/pcie-xilinx-nwl.c\n\nand make yours match spacing, capitalization, and style (imperative\nsentence).\n\nAlso waiting for ack from Michal.\n\nOn Fri, Sep 08, 2017 at 05:53:03PM +0530, Ravi Shankar Jonnalagadda wrote:\n> Enabling Root DMA interrupts\n> \n> Adding Root DMA translations to bridge for Register Access\n> \n> Signed-off-by: Ravi Shankar Jonnalagadda \n> Signed-off-by: RaviKiran Gummaluri \n> ---\n> drivers/pci/host/pcie-xilinx-nwl.c | 15 +++++++++++++++\n> 1 file changed, 15 insertions(+)\n> \n> diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c\n> index eec641a..5766582 100644\n> --- a/drivers/pci/host/pcie-xilinx-nwl.c\n> +++ b/drivers/pci/host/pcie-xilinx-nwl.c\n> @@ -39,6 +39,11 @@\n> #define E_ECAM_CONTROL\t\t\t0x00000228\n> #define E_ECAM_BASE_LO\t\t\t0x00000230\n> #define E_ECAM_BASE_HI\t\t\t0x00000234\n> +#define E_DREG_CTRL\t\t\t0x00000288\n> +#define E_DREG_BASE_LO\t\t\t0x00000290\n> +\n> +#define DREG_DMA_EN\t\t\tBIT(0)\n> +#define DREG_DMA_BASE_LO\t\t0xFD0F0000\n> \n> /* Ingress - address translations */\n> #define I_MSII_CAPABILITIES\t\t0x00000300\n> @@ -57,6 +62,10 @@\n> #define MSGF_MSI_STATUS_HI\t\t0x00000444\n> #define MSGF_MSI_MASK_LO\t\t0x00000448\n> #define MSGF_MSI_MASK_HI\t\t0x0000044C\n> +/* Root DMA Interrupt register */\n> +#define MSGF_DMA_MASK\t\t\t0x00000464\n> +\n> +#define MSGF_INTR_EN\t\t\tBIT(0)\n> \n> /* Msg filter mask bits */\n> #define CFG_ENABLE_PM_MSG_FWD\t\tBIT(1)\n> @@ -766,6 +775,12 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)\n> \tnwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &\n> \t\t\t MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);\n> \n> +\t/* Enabling DREG translations */\n> +\tnwl_bridge_writel(pcie, DREG_DMA_EN, E_DREG_CTRL);\n> +\tnwl_bridge_writel(pcie, DREG_DMA_BASE_LO, E_DREG_BASE_LO);\n> +\t/* Enabling Root DMA interrupts */\n> +\tnwl_bridge_writel(pcie, MSGF_INTR_EN, MSGF_DMA_MASK);\n> +\n> \t/* Enable all legacy interrupts */\n> \tnwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);\n> \n> -- \n> 2.7.4\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxY6028BFz9s82\n\tfor ;\n\tWed, 20 Sep 2017 05:36:40 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751374AbdISTgi (ORCPT );\n\tTue, 19 Sep 2017 15:36:38 -0400","from mail.kernel.org ([198.145.29.99]:46666 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750733AbdISTgh (ORCPT );\n\tTue, 19 Sep 2017 15:36:37 -0400","from localhost (unknown [69.55.156.165])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 4A5B3218F8;\n\tTue, 19 Sep 2017 19:36:36 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 4A5B3218F8","Date":"Tue, 19 Sep 2017 14:36:35 -0500","From":"Bjorn Helgaas ","To":"Ravi Shankar Jonnalagadda ","Cc":"vinod.koul@intel.com, robh+dt@kernel.org, mark.rutland@arm.com,\n\tmichal.simek@xilinx.com, soren.brinkmann@xilinx.com,\n\tdan.j.williams@intel.com, bhelgaas@google.com, vjonnal@xilinx.com,\n\tlorenzo.pieralisi@arm.com, bharat.kumar.gogada@xilinx.com,\n\tdmaengine@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tlinux-pci@vger.kernel.org, rgummal@xilinx.com","Subject":"Re: [PATCH v2 1/5] PCI:xilinx-nwl: Enable Root DMA","Message-ID":"<20170919193635.GE22312@bhelgaas-glaptop.roam.corp.google.com>","References":"<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>\n\t<1504873388-29195-2-git-send-email-vjonnal@xilinx.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504873388-29195-2-git-send-email-vjonnal@xilinx.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}}]